forked from OSchip/llvm-project
[SelectionDAG] Expose the "getValidShiftAmount" helpers available. NFCI.
These are going to be useful in TargetLowering::SimplifyDemandedBits, so expose these helpers outside of SelectionDAG.cpp Also add an getValidShiftAmountConstant early-out to getValidMinimumShiftAmountConstant/getValidMaximumShiftAmountConstant so we can use them for scalar cases as well.
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@ -1671,6 +1671,23 @@ public:
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/// that element from the source vector.
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SDValue getSplatValue(SDValue V);
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/// If a SHL/SRA/SRL node \p V has a constant or splat constant shift amount
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/// that is less than the element bit-width of the shift node, return it.
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const APInt *getValidShiftAmountConstant(SDValue V,
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const APInt &DemandedElts) const;
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/// If a SHL/SRA/SRL node \p V has constant shift amounts that are all less
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/// than the element bit-width of the shift node, return the minimum value.
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const APInt *
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getValidMinimumShiftAmountConstant(SDValue V,
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const APInt &DemandedElts) const;
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/// If a SHL/SRA/SRL node \p V has constant shift amounts that are all less
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/// than the element bit-width of the shift node, return the maximum value.
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const APInt *
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getValidMaximumShiftAmountConstant(SDValue V,
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const APInt &DemandedElts) const;
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/// Match a binop + shuffle pyramid that represents a horizontal reduction
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/// over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p
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/// Extract. The reduction must use one of the opcodes listed in /p
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@ -2407,10 +2407,12 @@ SDValue SelectionDAG::getSplatValue(SDValue V) {
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return SDValue();
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}
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/// If a SHL/SRA/SRL node has a constant or splat constant shift amount that
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/// is less than the element bit-width of the shift node, return it.
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static const APInt *getValidShiftAmountConstant(SDValue V,
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const APInt &DemandedElts) {
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const APInt *
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SelectionDAG::getValidShiftAmountConstant(SDValue V,
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const APInt &DemandedElts) const {
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assert((V.getOpcode() == ISD::SHL || V.getOpcode() == ISD::SRL ||
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V.getOpcode() == ISD::SRA) &&
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"Unknown shift node");
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unsigned BitWidth = V.getScalarValueSizeInBits();
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if (ConstantSDNode *SA = isConstOrConstSplat(V.getOperand(1), DemandedElts)) {
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// Shifting more than the bitwidth is not valid.
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@ -2421,10 +2423,13 @@ static const APInt *getValidShiftAmountConstant(SDValue V,
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return nullptr;
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}
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/// If a SHL/SRA/SRL node has constant vector shift amounts that are all less
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/// than the element bit-width of the shift node, return the minimum value.
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static const APInt *
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getValidMinimumShiftAmountConstant(SDValue V, const APInt &DemandedElts) {
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const APInt *SelectionDAG::getValidMinimumShiftAmountConstant(
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SDValue V, const APInt &DemandedElts) const {
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assert((V.getOpcode() == ISD::SHL || V.getOpcode() == ISD::SRL ||
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V.getOpcode() == ISD::SRA) &&
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"Unknown shift node");
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if (const APInt *ValidAmt = getValidShiftAmountConstant(V, DemandedElts))
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return ValidAmt;
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unsigned BitWidth = V.getScalarValueSizeInBits();
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auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1));
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if (!BV)
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@ -2447,10 +2452,13 @@ getValidMinimumShiftAmountConstant(SDValue V, const APInt &DemandedElts) {
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return MinShAmt;
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}
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/// If a SHL/SRA/SRL node has constant vector shift amounts that are all less
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/// than the element bit-width of the shift node, return the maximum value.
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static const APInt *
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getValidMaximumShiftAmountConstant(SDValue V, const APInt &DemandedElts) {
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const APInt *SelectionDAG::getValidMaximumShiftAmountConstant(
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SDValue V, const APInt &DemandedElts) const {
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assert((V.getOpcode() == ISD::SHL || V.getOpcode() == ISD::SRL ||
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V.getOpcode() == ISD::SRA) &&
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"Unknown shift node");
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if (const APInt *ValidAmt = getValidShiftAmountConstant(V, DemandedElts))
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return ValidAmt;
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unsigned BitWidth = V.getScalarValueSizeInBits();
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auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1));
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if (!BV)
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