forked from OSchip/llvm-project
[X86] Don't scalarize v2f32->v2i64 strict_fp_to_sint/uint with avx512dq and not avx512vl.
We can pad the v2f32 with 0s up to v8f32 and use a v8f32->v8i64 operation. This is what we end up with on non-strict nodes except we don't pad with 0s since we don't care about exceptions.
This commit is contained in:
Craig Topper
parent
3badd17b69
commit
a135c4a2cf
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@ -1719,6 +1719,19 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32,
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Subtarget.hasVLX() ? Legal : Custom);
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if (Subtarget.hasDQI()) {
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// Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
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// v2f32 UINT_TO_FP is already custom under SSE2.
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assert(isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) &&
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isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) &&
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"Unexpected operation action!");
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// v2i64 FP_TO_S/UINT(v2f32) custom conversion.
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setOperationAction(ISD::FP_TO_SINT, MVT::v2f32, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::v2f32, Custom);
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setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2f32, Custom);
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setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2f32, Custom);
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}
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for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
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setOperationAction(ISD::SMAX, VT, Legal);
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setOperationAction(ISD::UMAX, VT, Legal);
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@ -1838,19 +1851,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
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setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
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if (Subtarget.hasDQI()) {
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// Fast v2f32 SINT_TO_FP( v2i64 ) custom conversion.
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// v2f32 UINT_TO_FP is already custom under SSE2.
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assert(isOperationCustom(ISD::UINT_TO_FP, MVT::v2f32) &&
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isOperationCustom(ISD::STRICT_UINT_TO_FP, MVT::v2f32) &&
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"Unexpected operation action!");
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// v2i64 FP_TO_S/UINT(v2f32) custom conversion.
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setOperationAction(ISD::FP_TO_SINT, MVT::v2f32, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::v2f32, Custom);
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setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2f32, Custom);
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setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2f32, Custom);
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}
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if (Subtarget.hasBWI()) {
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setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
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setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
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@ -20717,6 +20717,25 @@ SDValue X86TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
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}
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if (VT == MVT::v2i64 && SrcVT == MVT::v2f32) {
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if (!Subtarget.hasVLX()) {
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// Non-strict nodes without VLX can we widened to v4f32->v4i64 by type
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// legalizer and then widened again by vector op legalization.
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if (!IsStrict)
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return SDValue();
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SDValue Zero = DAG.getConstantFP(0.0, dl, MVT::v2f32);
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SDValue Tmp = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8f32,
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{Src, Zero, Zero, Zero});
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Tmp = DAG.getNode(Op.getOpcode(), dl, {MVT::v8i64, MVT::Other},
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{Op->getOperand(0), Tmp});
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SDValue Chain = Tmp.getValue(1);
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Tmp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Tmp,
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DAG.getIntPtrConstant(0, dl));
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if (IsStrict)
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return DAG.getMergeValues({Tmp, Chain}, dl);
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return Tmp;
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}
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assert(Subtarget.hasDQI() && Subtarget.hasVLX() && "Requires AVX512DQVL");
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SDValue Tmp = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32, Src,
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DAG.getUNDEF(MVT::v2f32));
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@ -685,26 +685,14 @@ define <2 x i64> @strict_vector_fptosi_v2f32_to_v2i64(<2 x float> %a) #0 {
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; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
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; AVX512VL-64-NEXT: retq
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;
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; AVX512DQ-32-LABEL: strict_vector_fptosi_v2f32_to_v2i64:
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; AVX512DQ-32: # %bb.0:
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; AVX512DQ-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[1],zero,zero,zero
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; AVX512DQ-32-NEXT: vcvttps2qq %ymm1, %zmm1
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; AVX512DQ-32-NEXT: vxorps %xmm2, %xmm2, %xmm2
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; AVX512DQ-32-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
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; AVX512DQ-32-NEXT: vcvttps2qq %ymm0, %zmm0
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; AVX512DQ-32-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX512DQ-32-NEXT: vzeroupper
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; AVX512DQ-32-NEXT: retl
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;
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; AVX512DQ-64-LABEL: strict_vector_fptosi_v2f32_to_v2i64:
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; AVX512DQ-64: # %bb.0:
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; AVX512DQ-64-NEXT: vcvttss2si %xmm0, %rax
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; AVX512DQ-64-NEXT: vmovq %rax, %xmm1
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; AVX512DQ-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; AVX512DQ-64-NEXT: vcvttss2si %xmm0, %rax
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; AVX512DQ-64-NEXT: vmovq %rax, %xmm0
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; AVX512DQ-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
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; AVX512DQ-64-NEXT: retq
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; AVX512DQ-LABEL: strict_vector_fptosi_v2f32_to_v2i64:
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; AVX512DQ: # %bb.0:
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; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
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; AVX512DQ-NEXT: vcvttps2qq %ymm0, %zmm0
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; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
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; AVX512DQ-NEXT: vzeroupper
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; AVX512DQ-NEXT: ret{{[l|q]}}
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;
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; AVX512VLDQ-LABEL: strict_vector_fptosi_v2f32_to_v2i64:
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; AVX512VLDQ: # %bb.0:
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@ -1016,26 +1004,14 @@ define <2 x i64> @strict_vector_fptoui_v2f32_to_v2i64(<2 x float> %a) #0 {
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; AVX512VL-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
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; AVX512VL-64-NEXT: retq
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;
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; AVX512DQ-32-LABEL: strict_vector_fptoui_v2f32_to_v2i64:
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; AVX512DQ-32: # %bb.0:
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; AVX512DQ-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[1],zero,zero,zero
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; AVX512DQ-32-NEXT: vcvttps2uqq %ymm1, %zmm1
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; AVX512DQ-32-NEXT: vxorps %xmm2, %xmm2, %xmm2
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; AVX512DQ-32-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
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; AVX512DQ-32-NEXT: vcvttps2uqq %ymm0, %zmm0
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; AVX512DQ-32-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX512DQ-32-NEXT: vzeroupper
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; AVX512DQ-32-NEXT: retl
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;
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; AVX512DQ-64-LABEL: strict_vector_fptoui_v2f32_to_v2i64:
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; AVX512DQ-64: # %bb.0:
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; AVX512DQ-64-NEXT: vcvttss2usi %xmm0, %rax
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; AVX512DQ-64-NEXT: vmovq %rax, %xmm1
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; AVX512DQ-64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; AVX512DQ-64-NEXT: vcvttss2usi %xmm0, %rax
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; AVX512DQ-64-NEXT: vmovq %rax, %xmm0
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; AVX512DQ-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
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; AVX512DQ-64-NEXT: retq
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; AVX512DQ-LABEL: strict_vector_fptoui_v2f32_to_v2i64:
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; AVX512DQ: # %bb.0:
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; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
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; AVX512DQ-NEXT: vcvttps2uqq %ymm0, %zmm0
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; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
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; AVX512DQ-NEXT: vzeroupper
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; AVX512DQ-NEXT: ret{{[l|q]}}
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;
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; AVX512VLDQ-LABEL: strict_vector_fptoui_v2f32_to_v2i64:
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; AVX512VLDQ: # %bb.0:
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@ -3976,14 +3976,30 @@ define <2 x i64> @constrained_vector_fptosi_v2i64_v2f32() #0 {
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; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; CHECK-NEXT: retq
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;
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; AVX-LABEL: constrained_vector_fptosi_v2i64_v2f32:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvttss2si {{.*}}(%rip), %rax
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; AVX-NEXT: vmovq %rax, %xmm0
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; AVX-NEXT: vcvttss2si {{.*}}(%rip), %rax
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; AVX-NEXT: vmovq %rax, %xmm1
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; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
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; AVX-NEXT: retq
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; AVX1-LABEL: constrained_vector_fptosi_v2i64_v2f32:
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; AVX1: # %bb.0: # %entry
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; AVX1-NEXT: vcvttss2si {{.*}}(%rip), %rax
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; AVX1-NEXT: vmovq %rax, %xmm0
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; AVX1-NEXT: vcvttss2si {{.*}}(%rip), %rax
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; AVX1-NEXT: vmovq %rax, %xmm1
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; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
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; AVX1-NEXT: retq
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;
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; AVX512F-LABEL: constrained_vector_fptosi_v2i64_v2f32:
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; AVX512F: # %bb.0: # %entry
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; AVX512F-NEXT: vcvttss2si {{.*}}(%rip), %rax
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; AVX512F-NEXT: vmovq %rax, %xmm0
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; AVX512F-NEXT: vcvttss2si {{.*}}(%rip), %rax
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; AVX512F-NEXT: vmovq %rax, %xmm1
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; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
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; AVX512F-NEXT: retq
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;
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; AVX512DQ-LABEL: constrained_vector_fptosi_v2i64_v2f32:
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; AVX512DQ: # %bb.0: # %entry
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; AVX512DQ-NEXT: vcvttps2qq {{.*}}(%rip), %zmm0
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; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
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; AVX512DQ-NEXT: vzeroupper
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; AVX512DQ-NEXT: retq
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entry:
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%result = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f32(
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<2 x float><float 42.0, float 43.0>,
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@ -4588,14 +4604,21 @@ define <2 x i64> @constrained_vector_fptoui_v2i64_v2f32() #0 {
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; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: constrained_vector_fptoui_v2i64_v2f32:
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; AVX512: # %bb.0: # %entry
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; AVX512-NEXT: vcvttss2usi {{.*}}(%rip), %rax
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; AVX512-NEXT: vmovq %rax, %xmm0
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; AVX512-NEXT: vcvttss2usi {{.*}}(%rip), %rax
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; AVX512-NEXT: vmovq %rax, %xmm1
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; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
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; AVX512-NEXT: retq
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; AVX512F-LABEL: constrained_vector_fptoui_v2i64_v2f32:
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; AVX512F: # %bb.0: # %entry
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; AVX512F-NEXT: vcvttss2usi {{.*}}(%rip), %rax
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; AVX512F-NEXT: vmovq %rax, %xmm0
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; AVX512F-NEXT: vcvttss2usi {{.*}}(%rip), %rax
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; AVX512F-NEXT: vmovq %rax, %xmm1
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; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
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; AVX512F-NEXT: retq
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;
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; AVX512DQ-LABEL: constrained_vector_fptoui_v2i64_v2f32:
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; AVX512DQ: # %bb.0: # %entry
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; AVX512DQ-NEXT: vcvttps2uqq {{.*}}(%rip), %zmm0
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; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
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; AVX512DQ-NEXT: vzeroupper
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; AVX512DQ-NEXT: retq
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entry:
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%result = call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f32(
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<2 x float><float 42.0, float 43.0>,
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