From a11be047696cf71bb76517d1c1d63fefa123b49b Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Fri, 19 Aug 2016 22:40:08 +0000 Subject: [PATCH] GlobalISel: support legalization of G_FCONSTANTs llvm-svn: 279341 --- llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 9 +++++++++ llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 5 +++++ llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp | 8 ++++++++ llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp | 1 + .../CodeGen/AArch64/GlobalISel/legalize-constant.mir | 3 +++ 5 files changed, 26 insertions(+) diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index daaf511fd744..0c15e1204a15 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -302,6 +302,15 @@ public: MachineInstrBuilder buildIntrinsic(ArrayRef Tys, Intrinsic::ID ID, unsigned Res, bool HasSideEffects); + /// Build and insert \p Res = G_FPTRUNC \p Ty \p Op + /// + /// G_FPTRUNC converts a floating-point value into one with a smaller type. + /// + /// \pre setBasicBlock or setMI must have been called. + /// + /// \return The newly created instruction. + MachineInstrBuilder buildFPTrunc(LLT Ty, unsigned Res, unsigned Op); + /// Build and insert \p Res = G_TRUNC \p Ty \p Op /// /// G_TRUNC extracts the low bits of a type. For a vector type each element is diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index aa64be5a4c3b..5ad758897236 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -211,6 +211,11 @@ MachineInstrBuilder MachineIRBuilder::buildTrunc(LLT Ty, unsigned Res, return buildInstr(TargetOpcode::G_TRUNC, Ty).addDef(Res).addUse(Op); } +MachineInstrBuilder MachineIRBuilder::buildFPTrunc(LLT Ty, unsigned Res, + unsigned Op) { + return buildInstr(TargetOpcode::G_FPTRUNC, Ty).addDef(Res).addUse(Op); +} + MachineInstrBuilder MachineIRBuilder::buildICmp(ArrayRef Tys, CmpInst::Predicate Pred, unsigned Res, unsigned Op0, diff --git a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp index 632d6292f9c4..9dc2bf8864eb 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp @@ -141,6 +141,14 @@ MachineLegalizeHelper::widenScalar(MachineInstr &MI, LLT WideTy) { MI.eraseFromParent(); return Legalized; } + case TargetOpcode::G_FCONSTANT: { + MIRBuilder.setInstr(MI); + unsigned DstExt = MRI.createGenericVirtualRegister(WideSize); + MIRBuilder.buildFConstant(WideTy, DstExt, *MI.getOperand(1).getFPImm()); + MIRBuilder.buildFPTrunc(MI.getType(), MI.getOperand(0).getReg(), DstExt); + MI.eraseFromParent(); + return Legalized; + } } } diff --git a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp index a06eee0973e3..b91d6040bb60 100644 --- a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp @@ -63,6 +63,7 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() { for (auto Ty : {s1, s8, s16}) setAction(TargetOpcode::G_CONSTANT, Ty, WidenScalar); + setAction(TargetOpcode::G_FCONSTANT, s16, WidenScalar); setAction(G_BR, LLT::unsized(), Legal); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir index 1cf0e6810700..355552eab54d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir @@ -53,7 +53,10 @@ body: | ; CHECK-LABEL: name: test_fconstant ; CHECK: %0(32) = G_FCONSTANT s32 float 1.000000e+00 ; CHECK: %1(64) = G_FCONSTANT s64 double 2.000000e+00 + ; CHECK: [[TMP:%[0-9]+]](32) = G_FCONSTANT s32 half 0xH0000 + ; CHECK; %2(16) = G_FPTRUNC s16 [[TMP]] %0(32) = G_FCONSTANT s32 float 1.0 %1(64) = G_FCONSTANT s64 double 2.0 + %2(16) = G_FCONSTANT s16 half 0.0 ...