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[AVR] Fix lifeness issues in the AVR backend 

This patch is a large number of small changes that should hopefully not
affect the generated machine code but are still important to get right
so that the machine verifier won't complain about them.

The llvm/test/CodeGen/AVR/pseudo/*.mir changes are also necessary
because without the liveins the used registers are considered undefined
by the machine verifier and it will complain about them.

Differential Revision: https://reviews.llvm.org/D97172
This commit is contained in:
Ayke van Laethem 2021-02-22 01:36:26 +01:00
parent 52bfe6605a
commit a1155ae64d
No known key found for this signature in database
GPG Key ID: E97FF5335DFDFDED
33 changed files with 48 additions and 14 deletions
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29
llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
View File

@ -1055,6 +1055,7 @@ bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
Register SrcLoReg, SrcHiReg;
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
bool DstIsUndef = MI.getOperand(0).isUndef();
bool SrcIsKill = MI.getOperand(1).isKill();
unsigned OpLo = AVR::STPtrRr;
unsigned OpHi = AVR::STDPtrQRr;
@ -1062,11 +1063,11 @@ bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
//:TODO: need to reverse this order like inw and stsw?
auto MIBLO = buildMI(MBB, MBBI, OpLo)
.addReg(DstReg)
.addReg(DstReg, getUndefRegState(DstIsUndef))
.addReg(SrcLoReg, getKillRegState(SrcIsKill));
auto MIBHI = buildMI(MBB, MBBI, OpHi)
.addReg(DstReg)
.addReg(DstReg, getUndefRegState(DstIsUndef))
.addImm(1)
.addReg(SrcHiReg, getKillRegState(SrcIsKill));
@ -1435,7 +1436,7 @@ bool AVRExpandPseudo::expand<AVR::LSLW4Rd>(Block &MBB, BlockIt MBBI) {
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstHiReg, getKillRegState(DstIsKill))
.addReg(DstLoReg, getKillRegState(DstIsKill));
.addReg(DstLoReg);
// SREG is implicitly dead.
MI1->getOperand(3).setIsDead();
@ -1453,7 +1454,7 @@ bool AVRExpandPseudo::expand<AVR::LSLW4Rd>(Block &MBB, BlockIt MBBI) {
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstHiReg, getKillRegState(DstIsKill))
.addReg(DstLoReg, getKillRegState(DstIsKill));
.addReg(DstLoReg);
if (ImpIsDead)
MI3->getOperand(3).setIsDead();
@ -1474,7 +1475,7 @@ bool AVRExpandPseudo::expand<AVR::LSLW8Rd>(Block &MBB, BlockIt MBBI) {
// mov Rh, Rl
buildMI(MBB, MBBI, AVR::MOVRdRr)
.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstLoReg, getKillRegState(DstIsKill));
.addReg(DstLoReg);
// clr Rl
auto MIBLO =
@ -1502,7 +1503,7 @@ bool AVRExpandPseudo::expand<AVR::LSLW12Rd>(Block &MBB, BlockIt MBBI) {
// mov Rh, Rl
buildMI(MBB, MBBI, AVR::MOVRdRr)
.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstLoReg, getKillRegState(DstIsKill));
.addReg(DstLoReg);
// swap Rh
buildMI(MBB, MBBI, AVR::SWAPRd)
@ -1595,7 +1596,7 @@ bool AVRExpandPseudo::expand<AVR::LSRW4Rd>(Block &MBB, BlockIt MBBI) {
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstLoReg, getKillRegState(DstIsKill))
.addReg(DstHiReg, getKillRegState(DstIsKill));
.addReg(DstHiReg);
// SREG is implicitly dead.
MI1->getOperand(3).setIsDead();
@ -1613,7 +1614,7 @@ bool AVRExpandPseudo::expand<AVR::LSRW4Rd>(Block &MBB, BlockIt MBBI) {
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstLoReg, getKillRegState(DstIsKill))
.addReg(DstHiReg, getKillRegState(DstIsKill));
.addReg(DstHiReg);
if (ImpIsDead)
MI3->getOperand(3).setIsDead();
@ -1747,7 +1748,7 @@ bool AVRExpandPseudo::expand<AVR::ASRW8Rd>(Block &MBB, BlockIt MBBI) {
// Move upper byte to lower byte.
buildMI(MBB, MBBI, AVR::MOVRdRr)
.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstHiReg, getKillRegState(DstIsKill));
.addReg(DstHiReg);
// Move the sign bit to the C flag.
buildMI(MBB, MBBI, AVR::ADDRdRr)
@ -1782,7 +1783,8 @@ bool AVRExpandPseudo::expand<AVR::LSLB7Rd>(Block &MBB, BlockIt MBBI) {
buildMI(MBB, MBBI, AVR::RORRd)
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstReg, getKillRegState(DstIsKill));
.addReg(DstReg, getKillRegState(DstIsKill))
->getOperand(3).setIsUndef(true);
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
@ -1819,7 +1821,8 @@ bool AVRExpandPseudo::expand<AVR::LSRB7Rd>(Block &MBB, BlockIt MBBI) {
buildMI(MBB, MBBI, AVR::ADCRdRr)
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstReg, getKillRegState(DstIsKill))
.addReg(DstReg, getKillRegState(DstIsKill));
.addReg(DstReg, getKillRegState(DstIsKill))
->getOperand(4).setIsUndef(true);
buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
@ -1958,8 +1961,8 @@ template <> bool AVRExpandPseudo::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) {
auto EOR = buildMI(MBB, MBBI, AVR::EORRdRr)
.addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
.addReg(DstHiReg, RegState::Kill)
.addReg(DstHiReg, RegState::Kill);
.addReg(DstHiReg, RegState::Kill | RegState::Undef)
.addReg(DstHiReg, RegState::Kill | RegState::Undef);
if (ImpIsDead)
EOR->getOperand(3).setIsDead();

2
llvm/lib/Target/AVR/AVRFrameLowering.cpp
View File

@ -362,7 +362,7 @@ MachineBasicBlock::iterator AVRFrameLowering::eliminateCallFramePseudoInstr(
New->getOperand(3).setIsDead();
BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP)
.addReg(AVR::R31R30, RegState::Kill);
.addReg(AVR::R31R30);
// Make sure the remaining stack stores are converted to real store
// instructions.

1
llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
View File

@ -14,6 +14,7 @@
name: test_adcwrdrr
body: |
bb.0.entry:
liveins: $r15r14, $r21r20, $sreg
; CHECK-LABEL: test_adcwrdrr

1
llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
View File

@ -14,6 +14,7 @@
name: test_addwrdrr
body: |
bb.0.entry:
liveins: $r15r14, $r21r20
; CHECK-LABEL: test_addwrdrr

1
llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
View File

@ -14,6 +14,7 @@
name: test_andiwrdrr
body: |
bb.0.entry:
liveins: $r17r16
; CHECK-LABEL: test_andiwrdrr

1
llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
View File

@ -14,6 +14,7 @@
name: test_andwrdrr
body: |
bb.0.entry:
liveins: $r15r14, $r21r20
; CHECK-LABEL: test_andwrdrr

1
llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir
View File

@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
liveins: $r15r14
; CHECK-LABEL: test

1
llvm/test/CodeGen/AVR/pseudo/COMWRd.mir
View File

@ -14,6 +14,7 @@
name: test_comwrd
body: |
bb.0.entry:
liveins: $r15r14
; CHECK-LABEL: test_comwrd

1
llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
View File

@ -14,6 +14,7 @@
name: test_cpcwrdrr
body: |
bb.0.entry:
liveins: $r21r20, $r23r22, $sreg
; CHECK-LABEL: test_cpcwrdrr

1
llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir
View File

@ -14,6 +14,7 @@
name: test_cpwrdrr
body: |
bb.0.entry:
liveins: $r15r14, $r21r20
; CHECK-LABEL: test_cpwrdrr

1
llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir
View File

@ -14,6 +14,7 @@
name: test_eorwrdrr
body: |
bb.0.entry:
liveins: $r15r14, $r21r20
; CHECK-LABEL: test_eorwrdrr

1
llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir
View File

@ -18,6 +18,7 @@ registers:
- { id: 0, class: _ }
body: |
bb.0.entry:
liveins: $r31r30
; CHECK-LABEL: test

1
llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
View File

@ -15,6 +15,7 @@ name: test_lddwrdptrq
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $r31r30
; CHECK-LABEL: test_lddwrdptrq

1
llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
View File

@ -15,6 +15,7 @@ name: test_ldwrdptr
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $r31r30
; CHECK-LABEL: test_ldwrdptr

1
llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
View File

@ -14,6 +14,7 @@
name: test_ldwrdptr
body: |
bb.0.entry:
liveins: $r31r30
; CHECK-LABEL: test_ldwrdptr

1
llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
View File

@ -14,6 +14,7 @@
name: test_ldwrdptrpd
body: |
bb.0.entry:
liveins: $r31r30
; CHECK-LABEL: test_ldwrdptrpd

1
llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
View File

@ -14,6 +14,7 @@
name: test_ldwrdptrpi
body: |
bb.0.entry:
liveins: $r31r30
; CHECK-LABEL: test_ldwrdptrpi

1
llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir
View File

@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
liveins: $r15r14
; CHECK-LABEL: test

1
llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir
View File

@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
liveins: $r15r14
; CHECK-LABEL: test

1
llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir
View File

@ -14,6 +14,7 @@
name: test_negwrd
body: |
bb.0.entry:
liveins: $r15r14
; CHECK-LABEL: test_negwrd

1
llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir
View File

@ -14,6 +14,7 @@
name: test_oriwrdrr
body: |
bb.0.entry:
liveins: $r21r20
; CHECK-LABEL: test_oriwrdrr

1
llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir
View File

@ -14,6 +14,7 @@
name: test_orwrdrr
body: |
bb.0.entry:
liveins: $r15r14, $r21r20
; CHECK-LABEL: test_orwrdrr

1
llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir
View File

@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
liveins: $r15r14
; CHECK-LABEL: test

1
llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
View File

@ -14,6 +14,7 @@
name: test_sbciwrdk
body: |
bb.0.entry:
liveins: $r21r20, $sreg
; CHECK-LABEL: test_sbciwrdk

1
llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
View File

@ -14,6 +14,7 @@
name: test_sbcwrdrr
body: |
bb.0.entry:
liveins: $r15r14, $r21r20, $sreg
; CHECK-LABEL: test_sbcwrdrr

1
llvm/test/CodeGen/AVR/pseudo/SEXT.mir
View File

@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
liveins: $r31
; CHECK-LABEL: test

1
llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir
View File

@ -14,6 +14,7 @@
name: test_stswkrr
body: |
bb.0.entry:
liveins: $r31r30
; CHECK-LABEL: test_stswkrr

1
llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
View File

@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
liveins: $r31r30
; CHECK-LABEL: test

1
llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
View File

@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
liveins: $r31r30
; CHECK-LABEL: test

1
llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir
View File

@ -14,6 +14,7 @@
name: test_stwptrrr
body: |
bb.0.entry:
liveins: $r31r30, $r17r16
; CHECK-LABEL: test_stwptrrr

1
llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
View File

@ -14,6 +14,7 @@
name: test_subiwrdrr
body: |
bb.0.entry:
liveins: $r21r20
; CHECK-LABEL: test_subiwrdrr

1
llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
View File

@ -14,6 +14,7 @@
name: test_subwrdrr
body: |
bb.0.entry:
liveins: $r21r20, $r15r14
; CHECK-LABEL: test_subwrdrr

1
llvm/test/CodeGen/AVR/pseudo/ZEXT.mir
View File

@ -12,6 +12,7 @@
name: test
body: |
bb.0.entry:
liveins: $r31
; CHECK-LABEL: test