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Some minor cleanups: 

1. Compute action in X86SelectSelect based on MVT instead of type.
2. Use TLI.getValueType(..) instead of MVT::getVT(..) because the former
   handles pointers and the later doesn't.
3. Don't pass TLI into isTypeLegal, since it already has access to it as 
   an ivar.

#2 gives fast isel some minor new functionality: handling load/stores of
pointers.

llvm-svn: 57552
This commit is contained in:
Chris Lattner 2008-10-15 05:07:36 +00:00
parent 74e012839d
commit a0f9d4972f
1 changed files with 30 additions and 40 deletions
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70
llvm/lib/Target/X86/X86FastISel.cpp
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@ -126,19 +126,15 @@ private:
(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
} }
bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT, bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
bool AllowI1 = false);
}; };
bool X86FastISel::isTypeLegal(const Type *Ty, const TargetLowering &TLI, bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
MVT &VT, bool AllowI1) { VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
if (VT == MVT::Other || !VT.isSimple()) if (VT == MVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail. // Unhandled type. Halt "fast" selection and bail.
return false; return false;
if (VT == MVT::iPTR)
// Use pointer type.
VT = TLI.getPointerTy();
// For now, require SSE/SSE2 for performing floating-point operations, // For now, require SSE/SSE2 for performing floating-point operations,
// since x87 requires additional work. // since x87 requires additional work.
if (VT == MVT::f64 && !X86ScalarSSEf64) if (VT == MVT::f64 && !X86ScalarSSEf64)
@ -484,7 +480,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
/// X86SelectStore - Select and emit code to implement store instructions. /// X86SelectStore - Select and emit code to implement store instructions.
bool X86FastISel::X86SelectStore(Instruction* I) { bool X86FastISel::X86SelectStore(Instruction* I) {
MVT VT; MVT VT;
if (!isTypeLegal(I->getOperand(0)->getType(), TLI, VT)) if (!isTypeLegal(I->getOperand(0)->getType(), VT))
return false; return false;
unsigned Val = getRegForValue(I->getOperand(0)); unsigned Val = getRegForValue(I->getOperand(0));
if (Val == 0) if (Val == 0)
@ -502,7 +498,7 @@ bool X86FastISel::X86SelectStore(Instruction* I) {
/// ///
bool X86FastISel::X86SelectLoad(Instruction *I) { bool X86FastISel::X86SelectLoad(Instruction *I) {
MVT VT; MVT VT;
if (!isTypeLegal(I->getType(), TLI, VT)) if (!isTypeLegal(I->getType(), VT))
return false; return false;
X86AddressMode AM; X86AddressMode AM;
@ -527,7 +523,6 @@ static unsigned X86ChooseCmpOpcode(MVT VT) {
case MVT::f32: return X86::UCOMISSrr; case MVT::f32: return X86::UCOMISSrr;
case MVT::f64: return X86::UCOMISDrr; case MVT::f64: return X86::UCOMISDrr;
} }
} }
/// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
@ -579,7 +574,7 @@ bool X86FastISel::X86SelectCmp(Instruction *I) {
CmpInst *CI = cast<CmpInst>(I); CmpInst *CI = cast<CmpInst>(I);
MVT VT; MVT VT;
if (!isTypeLegal(I->getOperand(0)->getType(), TLI, VT)) if (!isTypeLegal(I->getOperand(0)->getType(), VT))
return false; return false;
unsigned ResultReg = createResultReg(&X86::GR8RegClass); unsigned ResultReg = createResultReg(&X86::GR8RegClass);
@ -784,8 +779,8 @@ bool X86FastISel::X86SelectShift(Instruction *I) {
return false; return false;
} }
MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
if (VT == MVT::Other || !isTypeLegal(I->getType(), TLI, VT)) if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
return false; return false;
unsigned Op0Reg = getRegForValue(I->getOperand(0)); unsigned Op0Reg = getRegForValue(I->getOperand(0));
@ -818,29 +813,25 @@ bool X86FastISel::X86SelectShift(Instruction *I) {
} }
bool X86FastISel::X86SelectSelect(Instruction *I) { bool X86FastISel::X86SelectSelect(Instruction *I) {
const Type *Ty = I->getType(); MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
if (isa<PointerType>(Ty)) if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
Ty = TD.getIntPtrType(); return false;
unsigned Opc = 0; unsigned Opc = 0;
const TargetRegisterClass *RC = NULL; const TargetRegisterClass *RC = NULL;
if (Ty == Type::Int16Ty) { if (VT.getSimpleVT() == MVT::i16) {
Opc = X86::CMOVE16rr; Opc = X86::CMOVE16rr;
RC = &X86::GR16RegClass; RC = &X86::GR16RegClass;
} else if (Ty == Type::Int32Ty) { } else if (VT.getSimpleVT() == MVT::i32) {
Opc = X86::CMOVE32rr; Opc = X86::CMOVE32rr;
RC = &X86::GR32RegClass; RC = &X86::GR32RegClass;
} else if (Ty == Type::Int64Ty) { } else if (VT.getSimpleVT() == MVT::i64) {
Opc = X86::CMOVE64rr; Opc = X86::CMOVE64rr;
RC = &X86::GR64RegClass; RC = &X86::GR64RegClass;
} else { } else {
return false; return false;
} }
MVT VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
if (VT == MVT::Other || !isTypeLegal(Ty, TLI, VT))
return false;
unsigned Op0Reg = getRegForValue(I->getOperand(0)); unsigned Op0Reg = getRegForValue(I->getOperand(0));
if (Op0Reg == 0) return false; if (Op0Reg == 0) return false;
unsigned Op1Reg = getRegForValue(I->getOperand(1)); unsigned Op1Reg = getRegForValue(I->getOperand(1));
@ -856,17 +847,16 @@ bool X86FastISel::X86SelectSelect(Instruction *I) {
} }
bool X86FastISel::X86SelectFPExt(Instruction *I) { bool X86FastISel::X86SelectFPExt(Instruction *I) {
if (Subtarget->hasSSE2()) { // fpext from float to double.
if (I->getType() == Type::DoubleTy) { if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) {
Value *V = I->getOperand(0); Value *V = I->getOperand(0);
if (V->getType() == Type::FloatTy) { if (V->getType() == Type::FloatTy) {
unsigned OpReg = getRegForValue(V); unsigned OpReg = getRegForValue(V);
if (OpReg == 0) return false; if (OpReg == 0) return false;
unsigned ResultReg = createResultReg(X86::FR64RegisterClass); unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg); BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
UpdateValueMap(I, ResultReg); UpdateValueMap(I, ResultReg);
return true; return true;
}
} }
} }
@ -958,7 +948,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
MVT RetVT; MVT RetVT;
if (RetTy == Type::VoidTy) if (RetTy == Type::VoidTy)
RetVT = MVT::isVoid; RetVT = MVT::isVoid;
else if (!isTypeLegal(RetTy, TLI, RetVT, true)) else if (!isTypeLegal(RetTy, RetVT, true))
return false; return false;
// Materialize callee address in a register. FIXME: GV address can be // Materialize callee address in a register. FIXME: GV address can be
@ -1012,7 +1002,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
const Type *ArgTy = (*i)->getType(); const Type *ArgTy = (*i)->getType();
MVT ArgVT; MVT ArgVT;
if (!isTypeLegal(ArgTy, TLI, ArgVT)) if (!isTypeLegal(ArgTy, ArgVT))
return false; return false;
unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
Flags.setOrigAlign(OriginalAlignment); Flags.setOrigAlign(OriginalAlignment);
@ -1065,7 +1055,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
Arg, ArgVT, Arg); Arg, ArgVT, Arg);
if (!Emitted) if (!Emitted)
Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
Arg, ArgVT, Arg); Arg, ArgVT, Arg);
if (!Emitted) if (!Emitted)
Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
Arg, ArgVT, Arg); Arg, ArgVT, Arg);
@ -1217,7 +1207,7 @@ X86FastISel::TargetSelectInstruction(Instruction *I) {
unsigned X86FastISel::TargetMaterializeConstant(Constant *C) { unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
MVT VT; MVT VT;
if (!isTypeLegal(C->getType(), TLI, VT)) if (!isTypeLegal(C->getType(), VT))
return false; return false;
// Get opcode and regclass of the output for the given load instruction. // Get opcode and regclass of the output for the given load instruction.