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[ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional. 

llvm-svn: 205892
This commit is contained in:
Bradley Smith 2014-04-09 14:44:31 +00:00
parent 70c6acbbfd
commit a0d7a9a12f
4 changed files with 67 additions and 13 deletions
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25
llvm/lib/Target/ARM64/ARM64InstrFormats.td
View File

@ -2431,7 +2431,13 @@ class am_unscaled_operand : Operand<i64> {
let ParserMatchClass = MemoryUnscaledOperand;
let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
}
class am_unscaled_wb_operand : Operand<i64> {
let PrintMethod = "printAMUnscaledWB";
let ParserMatchClass = MemoryUnscaledOperand;
let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
}
def am_unscaled : am_unscaled_operand;
def am_unscaled_wb: am_unscaled_wb_operand;
def am_unscaled8 : am_unscaled_operand,
ComplexPattern<i64, 2, "SelectAddrModeUnscaled8", []>;
def am_unscaled16 : am_unscaled_operand,
@ -2569,7 +2575,7 @@ class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
string asm>
: BaseLoadStorePreIdx<sz, V, opc,
(outs regtype:$Rt/*, GPR64sp:$wback*/),
(ins am_unscaled:$addr), asm, ""/*"$addr.base = $wback"*/>,
(ins am_unscaled_wb:$addr), asm, ""/*"$addr.base = $wback"*/>,
Sched<[WriteLD, WriteAdr]>;
let mayStore = 1, mayLoad = 0 in
@ -2577,7 +2583,7 @@ class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
string asm>
: BaseLoadStorePreIdx<sz, V, opc,
(outs/* GPR64sp:$wback*/),
(ins regtype:$Rt, am_unscaled:$addr),
(ins regtype:$Rt, am_unscaled_wb:$addr),
asm, ""/*"$addr.base = $wback"*/>,
Sched<[WriteAdr, WriteST]>;
} // hasSideEffects = 0
@ -2752,6 +2758,11 @@ def am_indexed32simm7 : Operand<i32> { // ComplexPattern<...>
let ParserMatchClass = MemoryIndexed32SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
def am_indexed32simm7_wb : Operand<i32> { // ComplexPattern<...>
let PrintMethod = "printAMIndexed32WB";
let ParserMatchClass = MemoryIndexed32SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
def MemoryIndexed64SImm7 : AsmOperandClass {
let Name = "MemoryIndexed64SImm7";
@ -2762,6 +2773,11 @@ def am_indexed64simm7 : Operand<i32> { // ComplexPattern<...>
let ParserMatchClass = MemoryIndexed64SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
def am_indexed64simm7_wb : Operand<i32> { // ComplexPattern<...>
let PrintMethod = "printAMIndexed64WB";
let ParserMatchClass = MemoryIndexed64SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
def MemoryIndexed128SImm7 : AsmOperandClass {
let Name = "MemoryIndexed128SImm7";
@ -2772,6 +2788,11 @@ def am_indexed128simm7 : Operand<i32> { // ComplexPattern<...>
let ParserMatchClass = MemoryIndexed128SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
def am_indexed128simm7_wb : Operand<i32> { // ComplexPattern<...>
let PrintMethod = "printAMIndexed128WB";
let ParserMatchClass = MemoryIndexed128SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
string asm>

22
llvm/lib/Target/ARM64/ARM64InstrInfo.td
View File

@ -965,13 +965,13 @@ def LDPQi : LoadPairOffset<0b10, 1, FPR128, am_indexed128simm7, "ldp">;
def LDPSWi : LoadPairOffset<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">;
// Pair (pre-indexed)
def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7, "ldp">;
def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7, "ldp">;
def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7, "ldp">;
def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7, "ldp">;
def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7, "ldp">;
def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "ldp">;
def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "ldp">;
def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "ldp">;
def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "ldp">;
def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "ldp">;
def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">;
def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7_wb, "ldpsw">;
// Pair (post-indexed)
def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
@ -1514,11 +1514,11 @@ def STPDi : StorePairOffset<0b01, 1, FPR64, am_indexed64simm7, "stp">;
def STPQi : StorePairOffset<0b10, 1, FPR128, am_indexed128simm7, "stp">;
// Pair (pre-indexed)
def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7, "stp">;
def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7, "stp">;
def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7, "stp">;
def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7, "stp">;
def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7, "stp">;
def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "stp">;
def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "stp">;
def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "stp">;
def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "stp">;
def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "stp">;
// Pair (pre-indexed)
def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;

13
llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
View File

@ -1200,6 +1200,19 @@ void ARM64InstPrinter::printAMIndexed(const MCInst *MI, unsigned OpNum,
O << ']';
}
void ARM64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
unsigned Scale, raw_ostream &O) {
const MCOperand MO1 = MI->getOperand(OpNum + 1);
O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
if (MO1.isImm()) {
O << ", #" << (MO1.getImm() * Scale);
} else {
assert(MO1.isExpr() && "Unexpected operand type!");
O << ", " << *MO1.getExpr();
}
O << ']';
}
void ARM64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
unsigned prfop = MI->getOperand(OpNum).getImm();

20
llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h
View File

@ -73,28 +73,48 @@ protected:
raw_ostream &O);
void printAMIndexed(const MCInst *MI, unsigned OpNum, unsigned Scale,
raw_ostream &O);
void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
raw_ostream &O);
void printAMIndexed128(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexed(MI, OpNum, 16, O);
}
void printAMIndexed128WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexedWB(MI, OpNum, 16, O);
}
void printAMIndexed64(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexed(MI, OpNum, 8, O);
}
void printAMIndexed64WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexedWB(MI, OpNum, 8, O);
}
void printAMIndexed32(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexed(MI, OpNum, 4, O);
}
void printAMIndexed32WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexedWB(MI, OpNum, 4, O);
}
void printAMIndexed16(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexed(MI, OpNum, 2, O);
}
void printAMIndexed16WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexedWB(MI, OpNum, 2, O);
}
void printAMIndexed8(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexed(MI, OpNum, 1, O);
}
void printAMIndexed8WB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexedWB(MI, OpNum, 1, O);
}
void printAMUnscaled(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexed(MI, OpNum, 1, O);
}
void printAMUnscaledWB(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
printAMIndexedWB(MI, OpNum, 1, O);
}
void printAMNoIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printImmScale4(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printImmScale8(const MCInst *MI, unsigned OpNum, raw_ostream &O);