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[Hexagon] Enable IAS in the Hexagon backend 

Reviewed By: kparzysz

Differential Revision: https://reviews.llvm.org/D123096
This commit is contained in:
Brad Smith 2022-06-03 18:15:12 -04:00
parent dd2362a8ba
commit a0bc67e555
9 changed files with 11 additions and 12 deletions
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1
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
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@ -34,5 +34,4 @@ HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) {
UsesELFSectionDirectiveForBSS = true;
ExceptionsType = ExceptionHandling::DwarfCFI;
UseLogicalShr = false;
UseIntegratedAssembler = false;
}

2
llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -no-integrated-as < %s | FileCheck %s
target triple = "hexagon"

2
llvm/test/CodeGen/Hexagon/inline-asm-i1.ll
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@ -1,6 +1,6 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: r[[REG0:[0-9]+]] = usr
; CHECK: [[REG0]] = insert(r{{[0-9]+}}, #1, #16)
; CHECK: [[REG0]] = insert(r{{[0-9]+}},#1,#16)
target triple = "hexagon"

2
llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -no-integrated-as < %s | FileCheck %s
; Check that constraints q and v are handled correctly.
; CHECK: q{{.}} = vgtw(v{{.}}.w,v{{.}}.w)

6
llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll
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@ -1,9 +1,9 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: r0 = #24
; CHECK-NEXT: r1 =
; CHECK: r1 =
; // R2 should be assigned a value from R3+.
; CHECK-NEXT: r2 = r{{[3-9]}}
; CHECK-NEXT: trap0
; CHECK: r2 = r{{[3-9]}}
; CHECK: trap0
target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
target triple = "hexagon"

2
llvm/test/CodeGen/Hexagon/v6-inlasm1.ll
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@ -1,5 +1,5 @@
; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s
; CHECK: vmemu(r{{[0-9]+}}) = v{{[0-9]*}};
; CHECK: vmemu(r{{[0-9]+}}+#0) = v{{[0-9]*}}
target triple = "hexagon"

2
llvm/test/CodeGen/Hexagon/v6-inlasm2.ll
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@ -1,5 +1,5 @@
; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s
; CHECK: vmemu(r{{[0-9]+}}) = v{{[0-9]*}};
; CHECK: vmemu(r{{[0-9]}}+#0) = v{{[0-9]*}}
target triple = "hexagon"

2
llvm/test/CodeGen/Hexagon/v6-inlasm3.ll
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@ -1,5 +1,5 @@
; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s
; CHECK: vmemu(r{{[0-9]+}}) = v{{[0-9]*}}
; CHECK: vmemu(r{{[0-9]}}+#0) = v{{[0-9]*}}
target triple = "hexagon"

4
llvm/test/CodeGen/Hexagon/v6vec-vprint.ll
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@ -1,5 +1,5 @@
; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s
; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s
; RUN: llc -no-integrated-as -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s
; RUN: llc -no-integrated-as -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s
; generate .long XXXX which is a vector debug print instruction.
; CHECK: .long 0x1dffe0
; CHECK: .long 0x1dffe0