forked from OSchip/llvm-project
Add asmprintergen support for the last X86 instruction that needs it: pcrelative calls.
llvm-svn: 15657
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@ -115,6 +115,10 @@ namespace {
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}
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}
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void printCallOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT) {
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printOp(MI->getOperand(OpNo), true); // Don't print "OFFSET".
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}
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void printMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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switch (VT) {
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@ -618,6 +622,9 @@ void X86AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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if (printInstruction(MI))
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return; // Printer was automatically generated
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MI->dump();
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abort();
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unsigned Opcode = MI->getOpcode();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const TargetInstrDescriptor &Desc = TII.get(Opcode);
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@ -29,6 +29,10 @@ def f32mem : X86MemOperand<f32>;
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def f64mem : X86MemOperand<f64>;
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def f80mem : X86MemOperand<f80>;
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// PCRelative calls need special operand formatting.
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let PrintMethod = "printCallOperand" in
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def calltarget : Operand<i32>;
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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@ -196,7 +200,7 @@ def JG : IBr<0x8F, (ops i32imm:$dst), "jg $dst">, TB;
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let isCall = 1 in
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// All calls clobber the non-callee saved registers...
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let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
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def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoMem, NoImm>; // FIXME: 'call' doesn't allow 'OFFSET'
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def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst">;
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def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call $dst">;
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def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call $dst">;
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}
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