forked from OSchip/llvm-project
[AMDGPU] gfx11 Decode wider instructions. NFC
Refactor to pass a templatized size parameter to the decoder to allow wider than 64bit decodes in a later patch. Contributors: Jay Foad <jay.foad@amd.com> Depends on D125261 Patch 5/N for upstreaming of AMDGPU gfx11 architecture. Reviewed By: dp Differential Revision: https://reviews.llvm.org/D125316
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@ -388,23 +388,6 @@ template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
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return Res;
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}
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DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
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MCInst &MI,
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uint64_t Inst,
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uint64_t Address) const {
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assert(MI.getOpcode() == 0);
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assert(MI.getNumOperands() == 0);
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MCInst TmpInst;
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HasLiteral = false;
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const auto SavedBytes = Bytes;
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if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
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MI = TmpInst;
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return MCDisassembler::Success;
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}
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Bytes = SavedBytes;
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return MCDisassembler::Fail;
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}
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// The disassembler is greedy, so we need to check FI operand value to
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// not parse a dpp if the correct literal is not set. For dpp16 the
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// autogenerated decoder checks the dpp literal
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@ -17,6 +17,7 @@
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/DataExtractor.h"
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#include <memory>
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@ -57,8 +58,21 @@ public:
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MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
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DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst,
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uint64_t Address) const;
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template <typename InsnType>
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DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst,
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uint64_t Address) const {
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assert(MI.getOpcode() == 0);
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assert(MI.getNumOperands() == 0);
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MCInst TmpInst;
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HasLiteral = false;
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const auto SavedBytes = Bytes;
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if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
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MI = TmpInst;
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return MCDisassembler::Success;
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}
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Bytes = SavedBytes;
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return MCDisassembler::Fail;
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}
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Optional<DecodeStatus> onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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