forked from OSchip/llvm-project
AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR v2s16
Handle it the same way as G_BUILD_VECTOR_TRUNC. Arguably only G_BUILD_VECTOR_TRUNC should be legal for this, but G_BUILD_VECTOR will probably be more convenient in most cases. llvm-svn: 371440
This commit is contained in:
Matt Arsenault
parent
fc910c507e
commit
a0933e6df7
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@ -713,14 +713,19 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
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}
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getActionDefinitionsBuilder(G_BUILD_VECTOR)
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.legalForCartesianProduct(AllS32Vectors, {S32})
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.legalForCartesianProduct(AllS64Vectors, {S64})
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.clampNumElements(0, V16S32, V16S32)
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.clampNumElements(0, V2S64, V8S64)
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.minScalarSameAs(1, 0)
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.legalIf(isRegisterType(0))
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.minScalarOrElt(0, S32);
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auto &BuildVector = getActionDefinitionsBuilder(G_BUILD_VECTOR)
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.legalForCartesianProduct(AllS32Vectors, {S32})
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.legalForCartesianProduct(AllS64Vectors, {S64})
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.clampNumElements(0, V16S32, V16S32)
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.clampNumElements(0, V2S64, V8S64);
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if (ST.hasScalarPackInsts())
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BuildVector.legalFor({V2S16, S32});
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BuildVector
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.minScalarSameAs(1, 0)
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.legalIf(isRegisterType(0))
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.minScalarOrElt(0, S32);
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if (ST.hasScalarPackInsts()) {
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getActionDefinitionsBuilder(G_BUILD_VECTOR_TRUNC)
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@ -1305,12 +1305,17 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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MI.eraseFromParent();
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return;
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}
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case AMDGPU::G_BUILD_VECTOR:
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case AMDGPU::G_BUILD_VECTOR_TRUNC: {
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Register DstReg = MI.getOperand(0).getReg();
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LLT DstTy = MRI.getType(DstReg);
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if (DstTy != LLT::vector(2, 16))
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break;
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assert(MI.getNumOperands() == 3 && empty(OpdMapper.getVRegs(0)));
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substituteSimpleCopyRegs(OpdMapper, 1);
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substituteSimpleCopyRegs(OpdMapper, 2);
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Register DstReg = MI.getOperand(0).getReg();
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const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI);
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if (DstBank == &AMDGPU::SGPRRegBank)
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break; // Can use S_PACK_* instructions.
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@ -1319,24 +1324,41 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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Register Lo = MI.getOperand(1).getReg();
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Register Hi = MI.getOperand(2).getReg();
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const LLT S32 = LLT::scalar(32);
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const RegisterBank *BankLo = getRegBank(Lo, MRI, *TRI);
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const RegisterBank *BankHi = getRegBank(Hi, MRI, *TRI);
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const LLT S32 = LLT::scalar(32);
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auto MaskLo = B.buildConstant(S32, 0xffff);
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MRI.setRegBank(MaskLo.getReg(0), *BankLo);
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Register ZextLo;
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Register ShiftHi;
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auto ShiftAmt = B.buildConstant(S32, 16);
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MRI.setRegBank(ShiftAmt.getReg(0), *BankHi);
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if (Opc == AMDGPU::G_BUILD_VECTOR) {
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ZextLo = B.buildZExt(S32, Lo).getReg(0);
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MRI.setRegBank(ZextLo, *BankLo);
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auto ShiftHi = B.buildShl(S32, Hi, ShiftAmt);
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MRI.setRegBank(ShiftHi.getReg(0), *BankHi);
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Register ZextHi = B.buildZExt(S32, Hi).getReg(0);
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MRI.setRegBank(ZextHi, *BankHi);
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auto Masked = B.buildAnd(S32, Lo, MaskLo);
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MRI.setRegBank(Masked.getReg(0), *BankLo);
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auto ShiftAmt = B.buildConstant(S32, 16);
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MRI.setRegBank(ShiftAmt.getReg(0), *BankHi);
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auto Or = B.buildOr(S32, Masked, ShiftHi);
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ShiftHi = B.buildShl(S32, ZextHi, ShiftAmt).getReg(0);
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MRI.setRegBank(ShiftHi, *BankHi);
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} else {
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Register MaskLo = B.buildConstant(S32, 0xffff).getReg(0);
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MRI.setRegBank(MaskLo, *BankLo);
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auto ShiftAmt = B.buildConstant(S32, 16);
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MRI.setRegBank(ShiftAmt.getReg(0), *BankHi);
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ShiftHi = B.buildShl(S32, Hi, ShiftAmt).getReg(0);
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MRI.setRegBank(ShiftHi, *BankHi);
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ZextLo = B.buildAnd(S32, Lo, MaskLo).getReg(0);
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MRI.setRegBank(ZextLo, *BankLo);
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}
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auto Or = B.buildOr(S32, ZextLo, ShiftHi);
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MRI.setRegBank(Or.getReg(0), *DstBank);
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B.buildBitcast(DstReg, Or);
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@ -1804,8 +1826,25 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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OpdsMapping[2] = nullptr;
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break;
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}
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case AMDGPU::G_MERGE_VALUES:
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case AMDGPU::G_BUILD_VECTOR:
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case AMDGPU::G_BUILD_VECTOR_TRUNC: {
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LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
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if (DstTy == LLT::vector(2, 16)) {
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unsigned DstSize = DstTy.getSizeInBits();
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unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
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unsigned Src0BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
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unsigned Src1BankID = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
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unsigned DstBankID = regBankUnion(Src0BankID, Src1BankID);
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OpdsMapping[0] = AMDGPU::getValueMapping(DstBankID, DstSize);
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OpdsMapping[1] = AMDGPU::getValueMapping(Src0BankID, SrcSize);
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OpdsMapping[2] = AMDGPU::getValueMapping(Src1BankID, SrcSize);
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break;
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}
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LLVM_FALLTHROUGH;
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}
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case AMDGPU::G_MERGE_VALUES:
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case AMDGPU::G_CONCAT_VECTORS: {
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unsigned Bank = isSALUMapping(MI) ?
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AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
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@ -1818,20 +1857,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize);
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break;
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}
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case AMDGPU::G_BUILD_VECTOR_TRUNC: {
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assert(MI.getNumOperands() == 3);
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unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
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unsigned Src0BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
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unsigned Src1BankID = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
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unsigned DstBankID = regBankUnion(Src0BankID, Src1BankID);
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OpdsMapping[0] = AMDGPU::getValueMapping(DstBankID, DstSize);
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OpdsMapping[1] = AMDGPU::getValueMapping(Src0BankID, SrcSize);
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OpdsMapping[2] = AMDGPU::getValueMapping(Src1BankID, SrcSize);
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break;
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}
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case AMDGPU::G_BITCAST:
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case AMDGPU::G_INTTOPTR:
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case AMDGPU::G_PTRTOINT:
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@ -0,0 +1,99 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: build_vector_v2s16_s32_ss
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: build_vector_v2s16_s32_ss
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
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; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s16) = G_TRUNC %0
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%3:_(s16) = G_TRUNC %1
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%4:_(<2 x s16>) = G_BUILD_VECTOR %2, %3
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...
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---
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name: build_vector_v2s16_s32_sv
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: build_vector_v2s16_s32_sv
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
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; CHECK: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
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; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s16)
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; CHECK: [[ZEXT1:%[0-9]+]]:vgpr(s32) = G_ZEXT [[TRUNC1]](s16)
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 16
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; CHECK: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[ZEXT1]], [[C]](s32)
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; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[ZEXT]], [[SHL]]
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; CHECK: [[BITCAST:%[0-9]+]]:vgpr(<2 x s16>) = G_BITCAST [[OR]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $vgpr0
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%2:_(s16) = G_TRUNC %0
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%3:_(s16) = G_TRUNC %1
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%4:_(<2 x s16>) = G_BUILD_VECTOR %2, %3
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...
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---
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name: build_vector_v2s16_s32_vs
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; CHECK-LABEL: name: build_vector_v2s16_s32_vs
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
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; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
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; CHECK: [[ZEXT:%[0-9]+]]:vgpr(s32) = G_ZEXT [[TRUNC]](s16)
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; CHECK: [[ZEXT1:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
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; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[ZEXT1]], [[C]](s32)
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; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[ZEXT]], [[SHL]]
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; CHECK: [[BITCAST:%[0-9]+]]:vgpr(<2 x s16>) = G_BITCAST [[OR]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $sgpr0
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%2:_(s16) = G_TRUNC %0
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%3:_(s16) = G_TRUNC %1
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%4:_(<2 x s16>) = G_BUILD_VECTOR %2, %3
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...
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---
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name: build_vector_v2s16_s32_vv
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: build_vector_v2s16_s32_vv
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
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; CHECK: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
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; CHECK: [[ZEXT:%[0-9]+]]:vgpr(s32) = G_ZEXT [[TRUNC]](s16)
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; CHECK: [[ZEXT1:%[0-9]+]]:vgpr(s32) = G_ZEXT [[TRUNC1]](s16)
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 16
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; CHECK: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[ZEXT1]], [[C]](s32)
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; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[ZEXT]], [[SHL]]
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; CHECK: [[BITCAST:%[0-9]+]]:vgpr(<2 x s16>) = G_BITCAST [[OR]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s16) = G_TRUNC %0
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%3:_(s16) = G_TRUNC %1
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%4:_(<2 x s16>) = G_BUILD_VECTOR %2, %3
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...
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