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[ARM] Minor refactoring to improve readability. NFC. 

llvm-svn: 249454
This commit is contained in:
Chad Rosier 2015-10-06 20:23:42 +00:00
parent 675418ebc0
commit a087fd21da
1 changed files with 14 additions and 13 deletions
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27
llvm/lib/Target/ARM/ARMISelLowering.cpp
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@ -9835,14 +9835,13 @@ static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
/// vcvt.s32.f32 d16, d16
/// becomes:
/// vcvt.s32.f32 d16, d16, #3
static SDValue PerformVCVTCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG,
const ARMSubtarget *Subtarget) {
SelectionDAG &DAG = DCI.DAG;
SDValue Op = N->getOperand(0);
if (!Subtarget->hasNEON())
return SDValue();
if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
Op.getOpcode() != ISD::FMUL)
SDValue Op = N->getOperand(0);
if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL)
return SDValue();
uint64_t C;
@ -9890,14 +9889,14 @@ static SDValue PerformVCVTCombine(SDNode *N,
/// vdiv.f32 d16, d17, d16
/// becomes:
/// vcvt.f32.s32 d16, d16, #3
static SDValue PerformVDIVCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG,
const ARMSubtarget *Subtarget) {
SelectionDAG &DAG = DCI.DAG;
if (!Subtarget->hasNEON())
return SDValue();
SDValue Op = N->getOperand(0);
unsigned OpOpcode = Op.getNode()->getOpcode();
if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
if (!N->getValueType(0).isVector() ||
(OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
return SDValue();
@ -10315,8 +10314,10 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
case ISD::FP_TO_UINT:
return PerformVCVTCombine(N, DCI.DAG, Subtarget);
case ISD::FDIV:
return PerformVDIVCombine(N, DCI.DAG, Subtarget);
case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
case ISD::SHL:
case ISD::SRA: