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Convert more tests to avoid llvm-as. 

llvm-svn: 81545
This commit is contained in:
Dan Gohman 2009-09-11 18:36:27 +00:00
parent 8b3a539579
commit a080159a7c
86 changed files with 112 additions and 181 deletions
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3
llvm/test/CodeGen/ARM/aliases.ll
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@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=arm-linux-gnueabi -o %t
; RUN: llc < %s -mtriple=arm-linux-gnueabi -o %t
; RUN: grep set %t | count 5
; RUN: grep globl %t | count 4
; RUN: grep weak %t | count 1

8
llvm/test/CodeGen/ARM/ifcvt6.ll
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@ -1,10 +1,6 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=arm -mtriple=arm-apple-darwin
; RUN: llvm-as < %s | \
; RUN: llc -march=arm -mtriple=arm-apple-darwin | \
; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep cmpne | count 1
; RUN: llvm-as < %s | \
; RUN: llc -march=arm -mtriple=arm-apple-darwin | \
; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep ldmhi | count 1
define void @foo(i32 %X, i32 %Y) {

11
llvm/test/CodeGen/ARM/ifcvt7.ll
View File

@ -1,13 +1,8 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=arm -mtriple=arm-apple-darwin
; RUN: llvm-as < %s | \
; RUN: llc -march=arm -mtriple=arm-apple-darwin | \
; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep cmpeq | count 1
; RUN: llvm-as < %s | \
; RUN: llc -march=arm -mtriple=arm-apple-darwin | \
; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep moveq | count 1
; RUN: llvm-as < %s | \
; RUN: llc -march=arm -mtriple=arm-apple-darwin | \
; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep ldmeq | count 1
; FIXME: Need post-ifcvt branch folding to get rid of the extra br at end of BB1.

5
llvm/test/CodeGen/ARM/ifcvt8.ll
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@ -1,7 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=arm -mtriple=arm-apple-darwin
; RUN: llvm-as < %s | \
; RUN: llc -march=arm -mtriple=arm-apple-darwin | \
; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin | \
; RUN: grep ldmne | count 1
%struct.SString = type { i8*, i32, i32 }

12
llvm/test/CodeGen/ARM/load-global.ll
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@ -1,14 +1,10 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=arm-apple-darwin -relocation-model=static | \
; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=static | \
; RUN: not grep {L_G\$non_lazy_ptr}
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | \
; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | \
; RUN: grep {L_G\$non_lazy_ptr} | count 2
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=arm-apple-darwin -relocation-model=pic | \
; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | \
; RUN: grep {ldr.*pc} | count 1
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=arm-linux-gnueabi -relocation-model=pic | \
; RUN: llc < %s -mtriple=arm-linux-gnueabi -relocation-model=pic | \
; RUN: grep {GOT} | count 1
@G = external global i32

2
llvm/test/CodeGen/CellSPU/and_ops.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep and %t1.s | count 234
; RUN: grep andc %t1.s | count 85
; RUN: grep andi %t1.s | count 37

2
llvm/test/CodeGen/CellSPU/call.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep brsl %t1.s | count 1
; RUN: grep brasl %t1.s | count 1
; RUN: grep stqd %t1.s | count 80

4
llvm/test/CodeGen/CellSPU/call_indirect.ll
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@ -1,5 +1,5 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu -mattr=large_mem > %t2.s
; RUN: grep bisl %t1.s | count 7
; RUN: grep ila %t1.s | count 1
; RUN: grep rotqby %t1.s | count 6

2
llvm/test/CodeGen/CellSPU/ctpop.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep cntb %t1.s | count 3
; RUN: grep andi %t1.s | count 3
; RUN: grep rotmi %t1.s | count 2

2
llvm/test/CodeGen/CellSPU/dp_farith.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep dfa %t1.s | count 2
; RUN: grep dfs %t1.s | count 2
; RUN: grep dfm %t1.s | count 6

2
llvm/test/CodeGen/CellSPU/eqv.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep eqv %t1.s | count 18
; RUN: grep xshw %t1.s | count 6
; RUN: grep xsbh %t1.s | count 3

2
llvm/test/CodeGen/CellSPU/extract_elt.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep shufb %t1.s | count 39
; RUN: grep ilhu %t1.s | count 27
; RUN: grep iohl %t1.s | count 27

2
llvm/test/CodeGen/CellSPU/fcmp32.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep fceq %t1.s | count 1
; RUN: grep fcmeq %t1.s | count 1

2
llvm/test/CodeGen/CellSPU/fcmp64.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
define i1 @fcmp_eq_setcc_f64(double %arg1, double %arg2) nounwind {
entry:

2
llvm/test/CodeGen/CellSPU/fdiv.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep frest %t1.s | count 2
; RUN: grep -w fi %t1.s | count 2
; RUN: grep -w fm %t1.s | count 2

2
llvm/test/CodeGen/CellSPU/fneg-fabs.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep 32768 %t1.s | count 2
; RUN: grep xor %t1.s | count 4
; RUN: grep and %t1.s | count 2

2
llvm/test/CodeGen/CellSPU/i64ops.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep xswd %t1.s | count 3
; RUN: grep xsbh %t1.s | count 1
; RUN: grep xshw %t1.s | count 2

2
llvm/test/CodeGen/CellSPU/i8ops.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; ModuleID = 'i8ops.bc'
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"

2
llvm/test/CodeGen/CellSPU/icmp16.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep ilh %t1.s | count 15
; RUN: grep ceqh %t1.s | count 29
; RUN: grep ceqhi %t1.s | count 13

2
llvm/test/CodeGen/CellSPU/icmp32.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep ila %t1.s | count 6
; RUN: grep ceq %t1.s | count 28
; RUN: grep ceqi %t1.s | count 12

2
llvm/test/CodeGen/CellSPU/icmp64.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep ceq %t1.s | count 20
; RUN: grep cgti %t1.s | count 12
; RUN: grep cgt %t1.s | count 16

2
llvm/test/CodeGen/CellSPU/icmp8.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep ceqb %t1.s | count 24
; RUN: grep ceqbi %t1.s | count 12
; RUN: grep clgtb %t1.s | count 11

2
llvm/test/CodeGen/CellSPU/immed16.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep "ilh" %t1.s | count 11
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"

2
llvm/test/CodeGen/CellSPU/immed32.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep ilhu %t1.s | count 8
; RUN: grep iohl %t1.s | count 6
; RUN: grep -w il %t1.s | count 3

2
llvm/test/CodeGen/CellSPU/immed64.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep lqa %t1.s | count 13
; RUN: grep ilhu %t1.s | count 15
; RUN: grep ila %t1.s | count 1

2
llvm/test/CodeGen/CellSPU/int2fp.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep csflt %t1.s | count 5
; RUN: grep cuflt %t1.s | count 1
; RUN: grep xshw %t1.s | count 2

2
llvm/test/CodeGen/CellSPU/intrinsics_branch.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep ceq %t1.s | count 30
; RUN: grep ceqb %t1.s | count 10
; RUN: grep ceqhi %t1.s | count 5

2
llvm/test/CodeGen/CellSPU/intrinsics_float.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep fa %t1.s | count 5
; RUN: grep fs %t1.s | count 5
; RUN: grep fm %t1.s | count 15

2
llvm/test/CodeGen/CellSPU/intrinsics_logical.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep and %t1.s | count 20
; RUN: grep andc %t1.s | count 5
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"

2
llvm/test/CodeGen/CellSPU/loads.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu | FileCheck %s
; RUN: llc < %s -march=cellspu | FileCheck %s
; ModuleID = 'loads.bc'
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"

2
llvm/test/CodeGen/CellSPU/mul_ops.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep mpy %t1.s | count 44
; RUN: grep mpyu %t1.s | count 4
; RUN: grep mpyh %t1.s | count 10

2
llvm/test/CodeGen/CellSPU/nand.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep nand %t1.s | count 90
; RUN: grep and %t1.s | count 94
; RUN: grep xsbh %t1.s | count 2

2
llvm/test/CodeGen/CellSPU/or_ops.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep and %t1.s | count 2
; RUN: grep orc %t1.s | count 85
; RUN: grep ori %t1.s | count 30

2
llvm/test/CodeGen/CellSPU/rotate_ops.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu -o %t1.s
; RUN: llc < %s -march=cellspu -o %t1.s
; RUN: grep rot %t1.s | count 85
; RUN: grep roth %t1.s | count 8
; RUN: grep roti.*5 %t1.s | count 1

2
llvm/test/CodeGen/CellSPU/select_bits.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep selb %t1.s | count 56
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"

2
llvm/test/CodeGen/CellSPU/sext128.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu | FileCheck %s
; RUN: llc < %s -march=cellspu | FileCheck %s
; ModuleID = 'sext128.bc'
target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:128:128-v128:128:128-a0:0:128-s0:128:128"

2
llvm/test/CodeGen/CellSPU/shift_ops.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep {shlh } %t1.s | count 9
; RUN: grep {shlhi } %t1.s | count 3
; RUN: grep {shl } %t1.s | count 9

2
llvm/test/CodeGen/CellSPU/sp_farith.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu -enable-unsafe-fp-math > %t1.s
; RUN: llc < %s -march=cellspu -enable-unsafe-fp-math > %t1.s
; RUN: grep fa %t1.s | count 2
; RUN: grep fs %t1.s | count 2
; RUN: grep fm %t1.s | count 6

2
llvm/test/CodeGen/CellSPU/stores.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep {stqd.*0(\$3)} %t1.s | count 4
; RUN: grep {stqd.*16(\$3)} %t1.s | count 4
; RUN: grep 16256 %t1.s | count 2

4
llvm/test/CodeGen/CellSPU/struct_1.ll
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@ -1,5 +1,5 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu -mattr=large_mem > %t2.s
; RUN: grep lqa %t1.s | count 5
; RUN: grep lqd %t1.s | count 11
; RUN: grep rotqbyi %t1.s | count 7

2
llvm/test/CodeGen/CellSPU/trunc.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep shufb %t1.s | count 19
; RUN: grep {ilhu.*1799} %t1.s | count 1
; RUN: grep {ilhu.*771} %t1.s | count 2

4
llvm/test/CodeGen/CellSPU/vec_const.ll
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@ -1,5 +1,5 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu -mattr=large_mem > %t2.s
; RUN: grep -w il %t1.s | count 3
; RUN: grep ilhu %t1.s | count 8
; RUN: grep -w ilh %t1.s | count 5

2
llvm/test/CodeGen/CellSPU/vecinsert.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep cbd %t1.s | count 5
; RUN: grep chd %t1.s | count 5
; RUN: grep cwd %t1.s | count 10

2
llvm/test/CodeGen/Generic/2002-04-14-UnexpectedUnsignedType.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as %s -o - | llc
; RUN: llc < %s
; This caused the backend to assert out with:
; SparcInstrInfo.cpp:103: failed assertion `0 && "Unexpected unsigned type"'

2
llvm/test/CodeGen/Generic/spillccr.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as %s -o - | llc
; RUN: llc < %s
; July 6, 2002 -- LLC Regression test
; This test case checks if the integer CC register %xcc (or %ccr)

3
llvm/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll
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@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
; RUN: grep {vspltish v.*, 10}
define void @test(<8 x i16>* %P) {

3
llvm/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll
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@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -combiner-alias-analysis | grep f5
; RUN: llc < %s -march=ppc32 -combiner-alias-analysis | grep f5
target datalayout = "E-p:32:32"
target triple = "powerpc-apple-darwin8.2.0"

14
llvm/test/CodeGen/PowerPC/Frames-small.ll
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@ -1,25 +1,21 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1
; RUN not grep {stw r31, 20(r1)} %t1
; RUN: grep {stwu r1, -16448(r1)} %t1
; RUN: grep {addi r1, r1, 16448} %t1
; RUN: llvm-as < %s | \
; RUN: llc < %s -march=ppc32 | \
; RUN: not grep {lwz r31, 20(r1)}
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \
; RUN: -o %t2
; RUN: grep {stw r31, 20(r1)} %t2
; RUN: grep {stwu r1, -16448(r1)} %t2
; RUN: grep {addi r1, r1, 16448} %t2
; RUN: grep {lwz r31, 20(r1)} %t2
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -o %t3
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -o %t3
; RUN: not grep {std r31, 40(r1)} %t3
; RUN: grep {stdu r1, -16496(r1)} %t3
; RUN: grep {addi r1, r1, 16496} %t3
; RUN: not grep {ld r31, 40(r1)} %t3
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \
; RUN: -o %t4
; RUN: grep {std r31, 40(r1)} %t4
; RUN: grep {stdu r1, -16496(r1)} %t4

6
llvm/test/CodeGen/PowerPC/buildvec_canonicalize.ll
View File

@ -1,11 +1,9 @@
; There should be exactly one vxor here.
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \
; RUN: llc < %s -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \
; RUN: grep vxor | count 1
; There should be exactly one vsplti here.
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \
; RUN: llc < %s -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \
; RUN: grep vsplti | count 1
define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {

14
llvm/test/CodeGen/PowerPC/fsqrt.ll
View File

@ -1,17 +1,13 @@
; fsqrt should be generated when the fsqrt feature is enabled, but not
; otherwise.
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
; RUN: grep {fsqrt f1, f1}
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
; RUN: grep {fsqrt f1, f1}
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
; RUN: grep {fsqrt f1, f1}
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
; RUN: not grep {fsqrt f1, f1}
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \
; RUN: not grep {fsqrt f1, f1}
declare double @llvm.sqrt.f64(double)

3
llvm/test/CodeGen/PowerPC/seteq-0.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | \
; RUN: grep {srwi r., r., 5}
define i32 @eq0(i32 %a) {

6
llvm/test/CodeGen/PowerPC/stfiwx.ll
View File

@ -1,9 +1,7 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=stfiwx -o %t1
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=stfiwx -o %t1
; RUN: grep stfiwx %t1
; RUN: not grep r1 %t1
; RUN: llvm-as < %s | \
; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-stfiwx \
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-stfiwx \
; RUN: -o %t2
; RUN: not grep stfiwx %t2
; RUN: grep r1 %t2

6
llvm/test/CodeGen/SPARC/ctpop.ll
View File

@ -1,9 +1,7 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=sparc -mattr=v9 -enable-sparc-v9-insts
; RUN: llc < %s -march=sparc -mattr=v9 -enable-sparc-v9-insts
; RUN: llc < %s -march=sparc -mattr=-v9 | \
; RUN: not grep popc
; RUN: llvm-as < %s | \
; RUN: llc -march=sparc -mattr=v9 -enable-sparc-v9-insts | grep popc
; RUN: llc < %s -march=sparc -mattr=v9 -enable-sparc-v9-insts | grep popc
declare i32 @llvm.ctpop.i32(i32)

12
llvm/test/CodeGen/Thumb2/load-global.ll
View File

@ -1,11 +1,7 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=thumbv7-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=STATIC
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=thumbv7-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DYNAMIC
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=PIC
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=thumbv7-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LINUX
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=STATIC
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DYNAMIC
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=PIC
; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LINUX
@G = external global i32

3
llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=x86 -mtriple=i686-apple-darwin8 -relocation-model=static > %t
; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin8 -relocation-model=static > %t
; RUN: grep {movl _last} %t | count 1
; RUN: grep {cmpl.*_last} %t | count 1

3
llvm/test/CodeGen/X86/2006-05-02-InstrSched1.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=x86 -relocation-model=static -stats |& \
; RUN: llc < %s -march=x86 -relocation-model=static -stats |& \
; RUN: grep asm-printer | grep 14
;
@size20 = external global i32 ; <i32*> [#uses=1]

3
llvm/test/CodeGen/X86/2006-05-08-InstrSched.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=x86 -relocation-model=static | not grep {subl.*%esp}
; RUN: llc < %s -march=x86 -relocation-model=static | not grep {subl.*%esp}
@A = external global i16* ; <i16**> [#uses=1]
@B = external global i32 ; <i32*> [#uses=1]

3
llvm/test/CodeGen/X86/aliases.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=i686-pc-linux-gnu -asm-verbose=false -o %t
; RUN: llc < %s -mtriple=i686-pc-linux-gnu -asm-verbose=false -o %t
; RUN: grep set %t | count 7
; RUN: grep globl %t | count 6
; RUN: grep weak %t | count 1

2
llvm/test/CodeGen/X86/extractelement-from-arg.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as %s -o - | llc -march=x86-64 -mattr=+sse2
; RUN: llc < %s -march=x86-64 -mattr=+sse2
define void @test(float* %R, <4 x float> %X) nounwind {
%tmp = extractelement <4 x float> %X, i32 3

4
llvm/test/CodeGen/X86/extractelement-load.ll
View File

@ -1,5 +1,5 @@
; RUN: llvm-as %s -o - | llc -march=x86 -mattr=+sse2 -mcpu=yonah | not grep movd
; RUN: llvm-as %s -o - | llc -march=x86-64 -mattr=+sse2 -mcpu=core2 | not grep movd
; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=yonah | not grep movd
; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | not grep movd
define i32 @t(<2 x i64>* %val) nounwind {
%tmp2 = load <2 x i64>* %val, align 16 ; <<2 x i64>> [#uses=1]

3
llvm/test/CodeGen/X86/fabs.ll
View File

@ -1,8 +1,7 @@
; Make sure this testcase codegens to the fabs instruction, not a call to fabsf
; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3,-sse | grep fabs\$ | \
; RUN: count 2
; RUN: llvm-as < %s | \
; RUN: llc -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
; RUN: grep fabs\$ | count 3
declare float @fabsf(float)

3
llvm/test/CodeGen/X86/fast-cc-callee-pops.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=x86 -x86-asm-syntax=intel -mcpu=yonah | grep {ret 20}
; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=yonah | grep {ret 20}
; Check that a fastcc function pops its stack variables before returning.

3
llvm/test/CodeGen/X86/fp-stack-ret.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=i686-apple-darwin8 -mcpu=yonah -march=x86 > %t
; RUN: llc < %s -mtriple=i686-apple-darwin8 -mcpu=yonah -march=x86 > %t
; RUN: grep fldl %t | count 1
; RUN: not grep xmm %t
; RUN: grep {sub.*esp} %t | count 1

2
llvm/test/CodeGen/X86/illegal-insert.ll
View File

@ -1,4 +1,4 @@
; RUN: llvm-as %s -o - | llc -march=x86-64
; RUN: llc < %s -march=x86-64
define <4 x double> @foo0(<4 x double> %t) {
%r = insertelement <4 x double> %t, double 2.3, i32 0

6
llvm/test/CodeGen/X86/sincos.ll
View File

@ -1,9 +1,7 @@
; Make sure this testcase codegens to the sin and cos instructions, not calls
; RUN: llvm-as < %s | \
; RUN: llc -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
; RUN: grep sin\$ | count 3
; RUN: llvm-as < %s | \
; RUN: llc -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \
; RUN: grep cos\$ | count 3
declare float @sinf(float)

6
llvm/test/CodeGen/X86/sse-load-ret.ll
View File

@ -1,7 +1,5 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=x86 -mcpu=yonah | not grep movss
; RUN: llvm-as < %s | \
; RUN: llc -march=x86 -mcpu=yonah | not grep xmm
; RUN: llc < %s -march=x86 -mcpu=yonah | not grep movss
; RUN: llc < %s -march=x86 -mcpu=yonah | not grep xmm
define double @test1(double* %P) {
%X = load double* %P ; <double> [#uses=1]

3
llvm/test/CodeGen/X86/sse_reload_fold.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -march=x86-64 -mattr=+64bit,+sse3 -print-failed-fuse-candidates |& \
; RUN: llc < %s -march=x86-64 -mattr=+64bit,+sse3 -print-failed-fuse-candidates |& \
; RUN: grep fail | count 1
declare float @test_f(float %f)

3
llvm/test/CodeGen/X86/x86-64-mem.ll
View File

@ -3,8 +3,7 @@
; RUN: grep %%rip %t1 | count 6
; RUN: grep movq %t1 | count 6
; RUN: grep leaq %t1 | count 1
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=static -o %t2
; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=static -o %t2
; RUN: grep movl %t2 | count 2
; RUN: grep movq %t2 | count 2

3
llvm/test/CodeGen/X86/x86-64-pic-1.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {call f@PLT} %t1
define void @g() {

3
llvm/test/CodeGen/X86/x86-64-pic-10.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {call g@PLT} %t1
@g = alias weak i32 ()* @f

3
llvm/test/CodeGen/X86/x86-64-pic-11.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {call __fixunsxfti@PLT} %t1
define i128 @f(x86_fp80 %a) nounwind {

3
llvm/test/CodeGen/X86/x86-64-pic-2.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {call f} %t1
; RUN: not grep {call f@PLT} %t1

3
llvm/test/CodeGen/X86/x86-64-pic-3.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {call f} %t1
; RUN: not grep {call f@PLT} %t1

3
llvm/test/CodeGen/X86/x86-64-pic-4.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {movq a@GOTPCREL(%rip),} %t1
@a = global i32 0

3
llvm/test/CodeGen/X86/x86-64-pic-5.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {movl a(%rip),} %t1
; RUN: not grep GOTPCREL %t1

3
llvm/test/CodeGen/X86/x86-64-pic-6.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {movl a(%rip),} %t1
; RUN: not grep GOTPCREL %t1

3
llvm/test/CodeGen/X86/x86-64-pic-7.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {movq f@GOTPCREL(%rip),} %t1
define void ()* @g() nounwind {

3
llvm/test/CodeGen/X86/x86-64-pic-8.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {leaq f(%rip),} %t1
; RUN: not grep GOTPCREL %t1

3
llvm/test/CodeGen/X86/x86-64-pic-9.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: llc -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1
; RUN: grep {leaq f(%rip),} %t1
; RUN: not grep GOTPCREL %t1

3
llvm/test/Transforms/PredicateSimplifier/2006-10-22-IntOr.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: opt -predsimplify -instcombine -simplifycfg -S > %t
; RUN: opt < %s -predsimplify -instcombine -simplifycfg -S > %t
; RUN: grep -v declare %t | not grep fail
; RUN: grep -v declare %t | grep pass | count 3

3
llvm/test/Transforms/PredicateSimplifier/2006-10-25-AddSetCC.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: opt -predsimplify -instcombine -simplifycfg -S | \
; RUN: opt < %s -predsimplify -instcombine -simplifycfg -S | \
; RUN: grep -v declare | grep pass | count 2
define i32 @test(i32 %x, i32 %y) {

3
llvm/test/Transforms/PredicateSimplifier/predsimplify.ll
View File

@ -1,5 +1,4 @@
; RUN: llvm-as < %s | \
; RUN: opt -predsimplify -instcombine -simplifycfg -S > %t
; RUN: opt < %s -predsimplify -instcombine -simplifycfg -S > %t
; RUN: grep -v declare %t | not grep fail
; RUN: grep -v declare %t | grep pass | count 4

3
llvm/test/Transforms/Reassociate/mul-factor3.ll
View File

@ -1,7 +1,6 @@
; This should be one add and two multiplies.
; RUN: llvm-as < %s | \
; RUN: opt -reassociate -instcombine -S > %t
; RUN: opt < %s -reassociate -instcombine -S > %t
; RUN: grep mul %t | count 2
; RUN: grep add %t | count 1

3
llvm/test/Transforms/Reassociate/mulfactor2.ll
View File

@ -1,7 +1,6 @@
; This should turn into one multiply and one add.
; RUN: llvm-as < %s | \
; RUN: opt -instcombine -reassociate -instcombine -S > %t
; RUN: opt < %s -instcombine -reassociate -instcombine -S > %t
; RUN: grep mul %t | count 1
; RUN: grep add %t | count 1

3
llvm/test/Transforms/Reassociate/shift-factor.ll
View File

@ -1,6 +1,5 @@
; There should be exactly one shift and one add left.
; RUN: llvm-as < %s | \
; RUN: opt -reassociate -instcombine -S > %t
; RUN: opt < %s -reassociate -instcombine -S > %t
; RUN: grep shl %t | count 1
; RUN: grep add %t | count 1

3
llvm/test/Transforms/TailCallElim/ackermann.ll
View File

@ -1,6 +1,5 @@
; This function contains two tail calls, which should be eliminated
; RUN: llvm-as < %s | \
; RUN: opt -tailcallelim -stats -disable-output |& grep {2 tailcallelim}
; RUN: opt < %s -tailcallelim -stats -disable-output |& grep {2 tailcallelim}
define i32 @Ack(i32 %M.1, i32 %N.1) {
entry: