forked from OSchip/llvm-project
[InstCombine] fold zext of masked bit set/clear
This does not solve PR17101, but it is one of the underlying diffs noted here: https://bugs.llvm.org/show_bug.cgi?id=17101#c8 We could ease the one-use checks for the 'clear' (no 'not' op) half of the transform, but I do not know if that asymmetry would make things better or worse. Proofs: https://rise4fun.com/Alive/uVB Name: masked bit set %sh1 = shl i32 1, %y %and = and i32 %sh1, %x %cmp = icmp ne i32 %and, 0 %r = zext i1 %cmp to i32 => %s = lshr i32 %x, %y %r = and i32 %s, 1 Name: masked bit clear %sh1 = shl i32 1, %y %and = and i32 %sh1, %x %cmp = icmp eq i32 %and, 0 %r = zext i1 %cmp to i32 => %xn = xor i32 %x, -1 %s = lshr i32 %xn, %y %r = and i32 %s, 1
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@ -922,10 +922,24 @@ Instruction *InstCombiner::transformZExtICmp(ICmpInst *Cmp, ZExtInst &Zext,
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}
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}
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// icmp ne A, B is equal to xor A, B when A and B only really have one bit.
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// It is also profitable to transform icmp eq into not(xor(A, B)) because that
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// may lead to additional simplifications.
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if (Cmp->isEquality() && Zext.getType() == Cmp->getOperand(0)->getType()) {
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// Test if a bit is clear/set using a shifted-one mask:
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// zext (icmp eq (and X, (1 << ShAmt)), 0) --> and (lshr (not X), ShAmt), 1
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// zext (icmp ne (and X, (1 << ShAmt)), 0) --> and (lshr X, ShAmt), 1
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Value *X, *ShAmt;
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if (Cmp->hasOneUse() && match(Cmp->getOperand(1), m_ZeroInt()) &&
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match(Cmp->getOperand(0),
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m_OneUse(m_c_And(m_Shl(m_One(), m_Value(ShAmt)), m_Value(X))))) {
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if (Cmp->getPredicate() == ICmpInst::ICMP_EQ)
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X = Builder.CreateNot(X);
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Value *Lshr = Builder.CreateLShr(X, ShAmt);
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Value *And1 = Builder.CreateAnd(Lshr, ConstantInt::get(X->getType(), 1));
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return replaceInstUsesWith(Zext, And1);
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}
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// icmp ne A, B is equal to xor A, B when A and B only really have one bit.
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// It is also profitable to transform icmp eq into not(xor(A, B)) because
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// that may lead to additional simplifications.
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if (IntegerType *ITy = dyn_cast<IntegerType>(Zext.getType())) {
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Value *LHS = Cmp->getOperand(0);
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Value *RHS = Cmp->getOperand(1);
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@ -177,11 +177,9 @@ declare void @use32(i32)
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define i32 @masked_bit_set(i32 %x, i32 %y) {
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; CHECK-LABEL: @masked_bit_set(
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; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SH1]], [[X:%.*]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
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; CHECK-NEXT: [[R:%.*]] = zext i1 [[CMP]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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%sh1 = shl i32 1, %y
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%and = and i32 %sh1, %x
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@ -192,11 +190,10 @@ define i32 @masked_bit_set(i32 %x, i32 %y) {
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define <2 x i32> @masked_bit_clear(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @masked_bit_clear(
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; CHECK-NEXT: [[SH1:%.*]] = shl <2 x i32> <i32 1, i32 1>, [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[SH1]], [[X:%.*]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[AND]], zeroinitializer
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; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[CMP]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[R]]
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; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
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; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i32> [[TMP1]], [[Y:%.*]]
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; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i32> [[TMP2]], <i32 1, i32 1>
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; CHECK-NEXT: ret <2 x i32> [[TMP3]]
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;
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%sh1 = shl <2 x i32> <i32 1, i32 1>, %y
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%and = and <2 x i32> %sh1, %x
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@ -208,11 +205,9 @@ define <2 x i32> @masked_bit_clear(<2 x i32> %x, <2 x i32> %y) {
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define <2 x i32> @masked_bit_set_commute(<2 x i32> %px, <2 x i32> %y) {
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; CHECK-LABEL: @masked_bit_set_commute(
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; CHECK-NEXT: [[X:%.*]] = srem <2 x i32> <i32 42, i32 3>, [[PX:%.*]]
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; CHECK-NEXT: [[SH1:%.*]] = shl <2 x i32> <i32 1, i32 1>, [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X]], [[SH1]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[AND]], zeroinitializer
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; CHECK-NEXT: [[R:%.*]] = zext <2 x i1> [[CMP]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[R]]
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; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 1, i32 1>
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; CHECK-NEXT: ret <2 x i32> [[TMP2]]
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;
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%x = srem <2 x i32> <i32 42, i32 3>, %px ; thwart complexity-based canonicalization
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%sh1 = shl <2 x i32> <i32 1, i32 1>, %y
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@ -225,11 +220,10 @@ define <2 x i32> @masked_bit_set_commute(<2 x i32> %px, <2 x i32> %y) {
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define i32 @masked_bit_clear_commute(i32 %px, i32 %y) {
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; CHECK-LABEL: @masked_bit_clear_commute(
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; CHECK-NEXT: [[X:%.*]] = srem i32 42, [[PX:%.*]]
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; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[X]], [[SH1]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
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; CHECK-NEXT: [[R:%.*]] = zext i1 [[CMP]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X]], -1
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], [[Y:%.*]]
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; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 1
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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%x = srem i32 42, %px ; thwart complexity-based canonicalization
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%sh1 = shl i32 1, %y
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@ -243,10 +237,9 @@ define i32 @masked_bit_set_use1(i32 %x, i32 %y) {
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; CHECK-LABEL: @masked_bit_set_use1(
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; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[SH1]])
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SH1]], [[X:%.*]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
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; CHECK-NEXT: [[R:%.*]] = zext i1 [[CMP]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], [[Y]]
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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%sh1 = shl i32 1, %y
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call void @use32(i32 %sh1)
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@ -256,6 +249,8 @@ define i32 @masked_bit_set_use1(i32 %x, i32 %y) {
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ret i32 %r
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}
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; Negative test
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define i32 @masked_bit_set_use2(i32 %x, i32 %y) {
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; CHECK-LABEL: @masked_bit_set_use2(
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; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]]
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@ -273,6 +268,8 @@ define i32 @masked_bit_set_use2(i32 %x, i32 %y) {
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ret i32 %r
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}
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; Negative test
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define i32 @masked_bit_set_use3(i32 %x, i32 %y) {
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; CHECK-LABEL: @masked_bit_set_use3(
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; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]]
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@ -294,10 +291,10 @@ define i32 @masked_bit_clear_use1(i32 %x, i32 %y) {
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; CHECK-LABEL: @masked_bit_clear_use1(
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; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[SH1]])
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[SH1]], [[X:%.*]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
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; CHECK-NEXT: [[R:%.*]] = zext i1 [[CMP]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], -1
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], [[Y]]
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; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 1
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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%sh1 = shl i32 1, %y
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call void @use32(i32 %sh1)
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@ -307,6 +304,8 @@ define i32 @masked_bit_clear_use1(i32 %x, i32 %y) {
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ret i32 %r
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}
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; Negative test
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define i32 @masked_bit_clear_use2(i32 %x, i32 %y) {
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; CHECK-LABEL: @masked_bit_clear_use2(
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; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]]
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@ -324,6 +323,8 @@ define i32 @masked_bit_clear_use2(i32 %x, i32 %y) {
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ret i32 %r
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}
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; Negative test
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define i32 @masked_bit_clear_use3(i32 %x, i32 %y) {
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; CHECK-LABEL: @masked_bit_clear_use3(
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; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]]
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@ -341,6 +342,8 @@ define i32 @masked_bit_clear_use3(i32 %x, i32 %y) {
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ret i32 %r
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}
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; Negative test
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define i32 @masked_bits_set(i32 %x, i32 %y) {
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; CHECK-LABEL: @masked_bits_set(
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; CHECK-NEXT: [[SH1:%.*]] = shl i32 3, [[Y:%.*]]
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ret i32 %r
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}
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; Negative test
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define i32 @div_bit_set(i32 %x, i32 %y) {
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; CHECK-LABEL: @div_bit_set(
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; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]]
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ret i32 %r
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}
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; Negative test
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define i32 @masked_bit_set_nonzero_cmp(i32 %x, i32 %y) {
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; CHECK-LABEL: @masked_bit_set_nonzero_cmp(
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; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]]
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ret i32 %r
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}
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; Negative test
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define i32 @masked_bit_wrong_pred(i32 %x, i32 %y) {
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; CHECK-LABEL: @masked_bit_wrong_pred(
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; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]]
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