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function names start with a lowercase letter; NFC 

llvm-svn: 262347
This commit is contained in:
Sanjay Patel 2016-03-01 16:17:48 +00:00
parent e309e1415d
commit 9fea531fec
1 changed files with 12 additions and 12 deletions
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24
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -21653,7 +21653,7 @@ X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// Utility function to emit xbegin specifying the start of an RTM region. /// Utility function to emit xbegin specifying the start of an RTM region.
static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB, static MachineBasicBlock *emitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
const TargetInstrInfo *TII) { const TargetInstrInfo *TII) {
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
@ -21710,7 +21710,7 @@ static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
// or XMM0_V32I8 in AVX all of this code can be replaced with that // or XMM0_V32I8 in AVX all of this code can be replaced with that
// in the .td file. // in the .td file.
static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB, static MachineBasicBlock *emitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
const TargetInstrInfo *TII) { const TargetInstrInfo *TII) {
unsigned Opc; unsigned Opc;
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
@ -21747,7 +21747,7 @@ static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
// FIXME: Custom handling because TableGen doesn't support multiple implicit // FIXME: Custom handling because TableGen doesn't support multiple implicit
// defs in an instruction pattern // defs in an instruction pattern
static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB, static MachineBasicBlock *emitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
const TargetInstrInfo *TII) { const TargetInstrInfo *TII) {
unsigned Opc; unsigned Opc;
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
@ -21782,7 +21782,7 @@ static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
return BB; return BB;
} }
static MachineBasicBlock *EmitWRPKRU(MachineInstr *MI, MachineBasicBlock *BB, static MachineBasicBlock *emitWRPKRU(MachineInstr *MI, MachineBasicBlock *BB,
const X86Subtarget &Subtarget) { const X86Subtarget &Subtarget) {
DebugLoc dl = MI->getDebugLoc(); DebugLoc dl = MI->getDebugLoc();
const TargetInstrInfo *TII = Subtarget.getInstrInfo(); const TargetInstrInfo *TII = Subtarget.getInstrInfo();
@ -21805,7 +21805,7 @@ static MachineBasicBlock *EmitWRPKRU(MachineInstr *MI, MachineBasicBlock *BB,
return BB; return BB;
} }
static MachineBasicBlock *EmitRDPKRU(MachineInstr *MI, MachineBasicBlock *BB, static MachineBasicBlock *emitRDPKRU(MachineInstr *MI, MachineBasicBlock *BB,
const X86Subtarget &Subtarget) { const X86Subtarget &Subtarget) {
DebugLoc dl = MI->getDebugLoc(); DebugLoc dl = MI->getDebugLoc();
const TargetInstrInfo *TII = Subtarget.getInstrInfo(); const TargetInstrInfo *TII = Subtarget.getInstrInfo();
@ -21823,7 +21823,7 @@ static MachineBasicBlock *EmitRDPKRU(MachineInstr *MI, MachineBasicBlock *BB,
return BB; return BB;
} }
static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB, static MachineBasicBlock *emitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
const X86Subtarget &Subtarget) { const X86Subtarget &Subtarget) {
DebugLoc dl = MI->getDebugLoc(); DebugLoc dl = MI->getDebugLoc();
const TargetInstrInfo *TII = Subtarget.getInstrInfo(); const TargetInstrInfo *TII = Subtarget.getInstrInfo();
@ -23337,7 +23337,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case X86::VPCMPESTRM128MEM: case X86::VPCMPESTRM128MEM:
assert(Subtarget.hasSSE42() && assert(Subtarget.hasSSE42() &&
"Target must have SSE4.2 or AVX features enabled"); "Target must have SSE4.2 or AVX features enabled");
return EmitPCMPSTRM(MI, BB, Subtarget.getInstrInfo()); return emitPCMPSTRM(MI, BB, Subtarget.getInstrInfo());
// String/text processing lowering. // String/text processing lowering.
case X86::PCMPISTRIREG: case X86::PCMPISTRIREG:
@ -23350,19 +23350,19 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case X86::VPCMPESTRIMEM: case X86::VPCMPESTRIMEM:
assert(Subtarget.hasSSE42() && assert(Subtarget.hasSSE42() &&
"Target must have SSE4.2 or AVX features enabled"); "Target must have SSE4.2 or AVX features enabled");
return EmitPCMPSTRI(MI, BB, Subtarget.getInstrInfo()); return emitPCMPSTRI(MI, BB, Subtarget.getInstrInfo());
// Thread synchronization. // Thread synchronization.
case X86::MONITOR: case X86::MONITOR:
return EmitMonitor(MI, BB, Subtarget); return emitMonitor(MI, BB, Subtarget);
// PKU feature // PKU feature
case X86::WRPKRU: case X86::WRPKRU:
return EmitWRPKRU(MI, BB, Subtarget); return emitWRPKRU(MI, BB, Subtarget);
case X86::RDPKRU: case X86::RDPKRU:
return EmitRDPKRU(MI, BB, Subtarget); return emitRDPKRU(MI, BB, Subtarget);
// xbegin // xbegin
case X86::XBEGIN: case X86::XBEGIN:
return EmitXBegin(MI, BB, Subtarget.getInstrInfo()); return emitXBegin(MI, BB, Subtarget.getInstrInfo());
case X86::VASTART_SAVE_XMM_REGS: case X86::VASTART_SAVE_XMM_REGS:
return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);