forked from OSchip/llvm-project
[SimplifyCFG] Regenerate preserve-branchweights.ll test. NFC
Regenerate this test using update_test_checks.py in preparation for an upcomming commit, to make it not depend on the names of instructions. llvm-svn: 346869
This commit is contained in:
John Brawn
parent
2b166c5044
commit
9fd8c20c4f
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@ -5,9 +5,20 @@ declare void @helper(i32)
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define void @test1(i1 %a, i1 %b) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
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; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
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; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[A_NOT]], [[C]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof !0
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; CHECK: Y:
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; CHECK-NEXT: call void @helper(i32 0)
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; CHECK-NEXT: ret void
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; CHECK: Z:
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; CHECK-NEXT: call void @helper(i32 1)
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %a, label %Y, label %X, !prof !0
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; CHECK: br i1 %or.cond, label %Z, label %Y, !prof !0
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X:
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%c = or i1 %b, false
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@ -26,11 +37,20 @@ Z:
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define void @fake_weights(i1 %a, i1 %b) {
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; CHECK-LABEL: @fake_weights(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
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; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
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; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[A_NOT]], [[C]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof !1
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; CHECK: Y:
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; CHECK-NEXT: call void @helper(i32 0)
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; CHECK-NEXT: ret void
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; CHECK: Z:
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; CHECK-NEXT: call void @helper(i32 1)
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %a, label %Y, label %X, !prof !12
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; CHECK: %or.cond = and i1 %a.not, %c
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; CHECK-NEXT: br i1 %or.cond, label %Z, label %Y, !prof !1
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; CHECK: Y:
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X:
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%c = or i1 %b, false
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br i1 %c, label %Z, label %Y, !prof !1
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@ -46,10 +66,19 @@ Z:
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define void @test2(i1 %a, i1 %b) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
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; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[A:%.*]], [[C]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof !2
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; CHECK: Y:
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; CHECK-NEXT: call void @helper(i32 0)
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; CHECK-NEXT: ret void
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; CHECK: Z:
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; CHECK-NEXT: call void @helper(i32 1)
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %a, label %X, label %Y, !prof !1
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; CHECK: br i1 %or.cond, label %Z, label %Y, !prof !2
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; CHECK-NOT: !prof
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X:
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%c = or i1 %b, false
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@ -66,7 +95,17 @@ Z:
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define void @test3(i1 %a, i1 %b) {
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; CHECK-LABEL: @test3(
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; CHECK: br i1 %or.cond, label %Z, label %Y, !prof !1
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
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; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[A:%.*]], [[C]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof !1
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; CHECK: Y:
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; CHECK-NEXT: call void @helper(i32 0)
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; CHECK-NEXT: ret void
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; CHECK: Z:
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; CHECK-NEXT: call void @helper(i32 1)
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %a, label %X, label %Y, !prof !1
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@ -85,7 +124,17 @@ Z:
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define void @test4(i1 %a, i1 %b) {
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; CHECK-LABEL: @test4(
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; CHECK: br i1 %or.cond, label %Z, label %Y, !prof !1
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
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; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[A:%.*]], [[C]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof !1
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; CHECK: Y:
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; CHECK-NEXT: call void @helper(i32 0)
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; CHECK-NEXT: ret void
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; CHECK: Z:
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; CHECK-NEXT: call void @helper(i32 1)
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %a, label %X, label %Y
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@ -104,17 +153,30 @@ Z:
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;; test5 - The case where it jumps to the default target will be removed.
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define void @test5(i32 %M, i32 %N) nounwind uwtable {
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i32 [[N:%.*]], label [[SW2:%.*]] [
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; CHECK-NEXT: i32 3, label [[SW_BB1:%.*]]
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; CHECK-NEXT: i32 2, label [[SW_BB:%.*]]
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; CHECK-NEXT: ], !prof !3
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; CHECK: sw.bb:
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; CHECK-NEXT: call void @helper(i32 0)
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; CHECK-NEXT: br label [[SW_EPILOG:%.*]]
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; CHECK: sw.bb1:
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; CHECK-NEXT: call void @helper(i32 1)
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; CHECK-NEXT: br label [[SW_EPILOG]]
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; CHECK: sw2:
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; CHECK-NEXT: call void @helper(i32 2)
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; CHECK-NEXT: br label [[SW_EPILOG]]
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; CHECK: sw.epilog:
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; CHECK-NEXT: ret void
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;
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entry:
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switch i32 %N, label %sw2 [
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i32 1, label %sw2
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i32 2, label %sw.bb
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i32 3, label %sw.bb1
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i32 1, label %sw2
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i32 2, label %sw.bb
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i32 3, label %sw.bb1
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], !prof !3
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; CHECK-LABEL: @test5(
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; CHECK: switch i32 %N, label %sw2 [
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; CHECK: i32 3, label %sw.bb1
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; CHECK: i32 2, label %sw.bb
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; CHECK: ], !prof !3
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sw.bb:
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call void @helper(i32 0)
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@ -136,18 +198,31 @@ sw.epilog:
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;; Then the second switch will be converted to a branch, finally, the first
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;; switch and the branch will be merged into a single switch.
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define void @test6(i32 %M, i32 %N) nounwind uwtable {
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; CHECK-LABEL: @test6(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i32 [[N:%.*]], label [[SW_EPILOG:%.*]] [
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; CHECK-NEXT: i32 3, label [[SW_BB1:%.*]]
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; CHECK-NEXT: i32 2, label [[SW_BB:%.*]]
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; CHECK-NEXT: i32 4, label [[SW_BB5:%.*]]
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; CHECK-NEXT: ], !prof !4
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; CHECK: sw.bb:
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; CHECK-NEXT: call void @helper(i32 0)
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; CHECK-NEXT: br label [[SW_EPILOG]]
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; CHECK: sw.bb1:
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; CHECK-NEXT: call void @helper(i32 1)
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; CHECK-NEXT: br label [[SW_EPILOG]]
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; CHECK: sw.bb5:
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; CHECK-NEXT: call void @helper(i32 3)
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; CHECK-NEXT: br label [[SW_EPILOG]]
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; CHECK: sw.epilog:
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; CHECK-NEXT: ret void
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;
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entry:
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switch i32 %N, label %sw2 [
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i32 1, label %sw2
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i32 2, label %sw.bb
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i32 3, label %sw.bb1
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i32 1, label %sw2
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i32 2, label %sw.bb
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i32 3, label %sw.bb1
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], !prof !4
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; CHECK-LABEL: @test6(
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; CHECK: switch i32 %N, label %sw.epilog
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; CHECK: i32 3, label %sw.bb1
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; CHECK: i32 2, label %sw.bb
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; CHECK: i32 4, label %sw.bb5
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; CHECK: ], !prof !4
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sw.bb:
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call void @helper(i32 0)
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@ -161,8 +236,8 @@ sw2:
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;; Here "case 2" is invalidated since the default case of the first switch
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;; does not include "case 2".
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switch i32 %N, label %sw.epilog [
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i32 2, label %sw.bb4
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i32 4, label %sw.bb5
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i32 2, label %sw.bb4
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i32 4, label %sw.bb5
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], !prof !5
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sw.bb4:
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@ -180,9 +255,19 @@ sw.epilog:
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;; This test is based on test1 but swapped the targets of the second branch.
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define void @test1_swap(i1 %a, i1 %b) {
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; CHECK-LABEL: @test1_swap(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
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; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[A:%.*]], [[C]]
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; CHECK-NEXT: br i1 [[OR_COND]], label [[Y:%.*]], label [[Z:%.*]], !prof !5
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; CHECK: Y:
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; CHECK-NEXT: call void @helper(i32 0)
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; CHECK-NEXT: ret void
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; CHECK: Z:
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; CHECK-NEXT: call void @helper(i32 1)
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %a, label %Y, label %X, !prof !0
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; CHECK: br i1 %or.cond, label %Y, label %Z, !prof !5
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X:
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%c = or i1 %b, false
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@ -199,10 +284,20 @@ Z:
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define void @test7(i1 %a, i1 %b) {
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; CHECK-LABEL: @test7(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
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; CHECK-NEXT: [[BRMERGE:%.*]] = or i1 [[A:%.*]], [[C]]
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; CHECK-NEXT: br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof !6
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; CHECK: Y:
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; CHECK-NEXT: call void @helper(i32 0)
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; CHECK-NEXT: ret void
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; CHECK: Z:
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; CHECK-NEXT: call void @helper(i32 1)
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; CHECK-NEXT: ret void
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;
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entry:
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%c = or i1 %b, false
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br i1 %a, label %Y, label %X, !prof !0
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; CHECK: br i1 %brmerge, label %Y, label %Z, !prof !6
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X:
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br i1 %c, label %Y, label %Z, !prof !6
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@ -219,114 +314,150 @@ Z:
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; Test basic folding to a conditional branch.
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define void @test8(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: @test8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LT:%.*]] = icmp slt i64 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: br i1 [[LT]], label [[A:%.*]], label [[B:%.*]], !prof !7
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; CHECK: a:
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; CHECK-NEXT: call void @helper(i32 0) #1
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; CHECK-NEXT: ret void
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; CHECK: b:
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; CHECK-NEXT: call void @helper(i32 1) #1
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; CHECK-NEXT: ret void
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;
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entry:
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%lt = icmp slt i64 %x, %y
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; CHECK: br i1 %lt, label %a, label %b, !prof !7
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%qux = select i1 %lt, i32 0, i32 2
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switch i32 %qux, label %bees [
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i32 0, label %a
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i32 1, label %b
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i32 2, label %b
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], !prof !7
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%lt = icmp slt i64 %x, %y
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%qux = select i1 %lt, i32 0, i32 2
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switch i32 %qux, label %bees [
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i32 0, label %a
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i32 1, label %b
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i32 2, label %b
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], !prof !7
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a:
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call void @helper(i32 0) nounwind
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ret void
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call void @helper(i32 0) nounwind
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ret void
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b:
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call void @helper(i32 1) nounwind
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ret void
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call void @helper(i32 1) nounwind
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ret void
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bees:
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call void @helper(i32 2) nounwind
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ret void
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call void @helper(i32 2) nounwind
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ret void
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}
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; Test edge splitting when the default target has icmp and unconditinal
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; branch
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define i1 @test9(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: @test9(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i32 [[X:%.*]], label [[BEES:%.*]] [
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; CHECK-NEXT: i32 0, label [[A:%.*]]
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; CHECK-NEXT: i32 1, label [[END:%.*]]
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; CHECK-NEXT: i32 2, label [[END]]
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; CHECK-NEXT: i32 92, label [[END]]
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; CHECK-NEXT: ], !prof !8
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; CHECK: a:
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; CHECK-NEXT: call void @helper(i32 0) #1
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; CHECK-NEXT: [[RETA:%.*]] = icmp slt i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: ret i1 [[RETA]]
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; CHECK: bees:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[RET:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[BEES]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
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; CHECK-NEXT: call void @helper(i32 2) #1
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; CHECK-NEXT: ret i1 [[RET]]
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;
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entry:
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switch i32 %x, label %bees [
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i32 0, label %a
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i32 1, label %end
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i32 2, label %end
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], !prof !7
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; CHECK: switch i32 %x, label %bees [
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; CHECK: i32 0, label %a
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; CHECK: i32 1, label %end
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; CHECK: i32 2, label %end
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; CHECK: i32 92, label %end
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; CHECK: ], !prof !8
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switch i32 %x, label %bees [
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i32 0, label %a
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i32 1, label %end
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i32 2, label %end
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], !prof !7
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a:
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call void @helper(i32 0) nounwind
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%reta = icmp slt i32 %x, %y
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ret i1 %reta
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call void @helper(i32 0) nounwind
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%reta = icmp slt i32 %x, %y
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ret i1 %reta
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bees:
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%tmp = icmp eq i32 %x, 92
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br label %end
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%tmp = icmp eq i32 %x, 92
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br label %end
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end:
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; CHECK: end:
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; CHECK: %ret = phi i1 [ true, %entry ], [ false, %bees ], [ true, %entry ], [ true, %entry ]
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%ret = phi i1 [ true, %entry ], [%tmp, %bees], [true, %entry]
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call void @helper(i32 2) nounwind
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ret i1 %ret
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%ret = phi i1 [ true, %entry ], [%tmp, %bees], [true, %entry]
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call void @helper(i32 2) nounwind
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ret i1 %ret
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}
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define void @test10(i32 %x) nounwind readnone ssp noredzone {
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; CHECK-LABEL: @test10(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -1
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; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
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; CHECK-NEXT: br i1 [[SWITCH]], label [[LOR_END:%.*]], label [[LOR_RHS:%.*]], !prof !9
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; CHECK: lor.rhs:
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; CHECK-NEXT: call void @helper(i32 1) #1
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; CHECK-NEXT: ret void
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; CHECK: lor.end:
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; CHECK-NEXT: call void @helper(i32 0) #1
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; CHECK-NEXT: ret void
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;
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entry:
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switch i32 %x, label %lor.rhs [
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i32 2, label %lor.end
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i32 1, label %lor.end
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i32 3, label %lor.end
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], !prof !7
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switch i32 %x, label %lor.rhs [
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i32 2, label %lor.end
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i32 1, label %lor.end
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i32 3, label %lor.end
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], !prof !7
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lor.rhs:
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call void @helper(i32 1) nounwind
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ret void
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call void @helper(i32 1) nounwind
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ret void
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lor.end:
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call void @helper(i32 0) nounwind
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ret void
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call void @helper(i32 0) nounwind
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ret void
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; CHECK-LABEL: @test10(
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; CHECK: %x.off = add i32 %x, -1
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; CHECK: %switch = icmp ult i32 %x.off, 3
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; CHECK: br i1 %switch, label %lor.end, label %lor.rhs, !prof !9
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}
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; Remove dead cases from the switch.
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define void @test11(i32 %x) nounwind {
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; CHECK-LABEL: @test11(
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; CHECK-NEXT: [[I:%.*]] = shl i32 [[X:%.*]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I]], 24
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; CHECK-NEXT: br i1 [[COND]], label [[C:%.*]], label [[A:%.*]], !prof !10
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; CHECK: a:
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; CHECK-NEXT: call void @helper(i32 0) #1
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; CHECK-NEXT: ret void
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; CHECK: c:
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; CHECK-NEXT: call void @helper(i32 2) #1
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; CHECK-NEXT: ret void
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;
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%i = shl i32 %x, 1
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switch i32 %i, label %a [
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i32 21, label %b
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i32 24, label %c
|
||||
i32 21, label %b
|
||||
i32 24, label %c
|
||||
], !prof !8
|
||||
; CHECK-LABEL: @test11(
|
||||
; CHECK: %cond = icmp eq i32 %i, 24
|
||||
; CHECK: br i1 %cond, label %c, label %a, !prof !10
|
||||
|
||||
a:
|
||||
call void @helper(i32 0) nounwind
|
||||
ret void
|
||||
call void @helper(i32 0) nounwind
|
||||
ret void
|
||||
b:
|
||||
call void @helper(i32 1) nounwind
|
||||
ret void
|
||||
call void @helper(i32 1) nounwind
|
||||
ret void
|
||||
c:
|
||||
call void @helper(i32 2) nounwind
|
||||
ret void
|
||||
call void @helper(i32 2) nounwind
|
||||
ret void
|
||||
}
|
||||
|
||||
;; test12 - Don't crash if the whole switch is removed
|
||||
define void @test12(i32 %M, i32 %N) nounwind uwtable {
|
||||
; CHECK-LABEL: @test12(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: call void @helper(i32 0)
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
switch i32 %N, label %sw.bb [
|
||||
i32 1, label %sw.bb
|
||||
i32 1, label %sw.bb
|
||||
], !prof !9
|
||||
; CHECK-LABEL: @test12(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: call void @helper
|
||||
; CHECK-NEXT: ret void
|
||||
|
||||
sw.bb:
|
||||
call void @helper(i32 0)
|
||||
|
|
@ -339,26 +470,27 @@ sw.epilog:
|
|||
;; If every case is dead, make sure they are all removed. This used to
|
||||
;; crash trying to merge the metadata.
|
||||
define void @test13(i32 %x) nounwind {
|
||||
; CHECK-LABEL: @test13(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: call void @helper(i32 0) #1
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
%i = shl i32 %x, 1
|
||||
switch i32 %i, label %a [
|
||||
i32 21, label %b
|
||||
i32 25, label %c
|
||||
i32 21, label %b
|
||||
i32 25, label %c
|
||||
], !prof !8
|
||||
; CHECK-LABEL: @test13(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: call void @helper
|
||||
; CHECK-NEXT: ret void
|
||||
|
||||
a:
|
||||
call void @helper(i32 0) nounwind
|
||||
ret void
|
||||
call void @helper(i32 0) nounwind
|
||||
ret void
|
||||
b:
|
||||
call void @helper(i32 1) nounwind
|
||||
ret void
|
||||
call void @helper(i32 1) nounwind
|
||||
ret void
|
||||
c:
|
||||
call void @helper(i32 2) nounwind
|
||||
ret void
|
||||
call void @helper(i32 2) nounwind
|
||||
ret void
|
||||
}
|
||||
|
||||
;; When folding branches to common destination, the updated branch weights
|
||||
|
|
@ -366,8 +498,24 @@ c:
|
|||
;; weights until they can fit into uint32.
|
||||
@max_regno = common global i32 0, align 4
|
||||
define void @test14(i32* %old, i32 %final) {
|
||||
; CHECK-LABEL: @test14
|
||||
; CHECK: br i1 %or.cond, label %for.exit, label %for.inc, !prof !11
|
||||
; CHECK-LABEL: @test14(
|
||||
; CHECK-NEXT: for.cond:
|
||||
; CHECK-NEXT: br label [[FOR_COND2:%.*]]
|
||||
; CHECK: for.cond2:
|
||||
; CHECK-NEXT: [[I_1:%.*]] = phi i32 [ [[INC19:%.*]], [[FOR_INC:%.*]] ], [ 0, [[FOR_COND:%.*]] ]
|
||||
; CHECK-NEXT: [[BIT_0:%.*]] = phi i32 [ [[SHL:%.*]], [[FOR_INC]] ], [ 1, [[FOR_COND]] ]
|
||||
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[BIT_0]], 0
|
||||
; CHECK-NEXT: [[V3:%.*]] = load i32, i32* @max_regno, align 4
|
||||
; CHECK-NEXT: [[CMP4:%.*]] = icmp eq i32 [[I_1]], [[V3]]
|
||||
; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[TOBOOL]], [[CMP4]]
|
||||
; CHECK-NEXT: br i1 [[OR_COND]], label [[FOR_EXIT:%.*]], label [[FOR_INC]], !prof !11
|
||||
; CHECK: for.inc:
|
||||
; CHECK-NEXT: [[SHL]] = shl i32 [[BIT_0]], 1
|
||||
; CHECK-NEXT: [[INC19]] = add nsw i32 [[I_1]], 1
|
||||
; CHECK-NEXT: br label [[FOR_COND2]]
|
||||
; CHECK: for.exit:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
for.cond:
|
||||
br label %for.cond2
|
||||
for.cond2:
|
||||
|
|
@ -392,7 +540,7 @@ for.exit:
|
|||
define i32 @HoistThenElseCodeToIf(i32 %n) {
|
||||
; CHECK-LABEL: @HoistThenElseCodeToIf(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 %n, 0
|
||||
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[N:%.*]], 0
|
||||
; CHECK-NEXT: [[DOT:%.*]] = select i1 [[TOBOOL]], i32 1, i32 234, !prof !12
|
||||
; CHECK-NEXT: ret i32 [[DOT]]
|
||||
;
|
||||
|
|
@ -416,8 +564,8 @@ return:
|
|||
define i32 @SimplifyCondBranchToCondBranch(i1 %cmpa, i1 %cmpb) {
|
||||
; CHECK-LABEL: @SimplifyCondBranchToCondBranch(
|
||||
; CHECK-NEXT: block1:
|
||||
; CHECK-NEXT: [[BRMERGE:%.*]] = or i1 %cmpa, %cmpb
|
||||
; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 %cmpa, i32 0, i32 2, !prof !13
|
||||
; CHECK-NEXT: [[BRMERGE:%.*]] = or i1 [[CMPA:%.*]], [[CMPB:%.*]]
|
||||
; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[CMPA]], i32 0, i32 2, !prof !13
|
||||
; CHECK-NEXT: [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof !14
|
||||
; CHECK-NEXT: ret i32 [[OUTVAL]]
|
||||
;
|
||||
|
|
@ -441,8 +589,8 @@ exit:
|
|||
define i32 @SimplifyCondBranchToCondBranchSwap(i1 %cmpa, i1 %cmpb) {
|
||||
; CHECK-LABEL: @SimplifyCondBranchToCondBranchSwap(
|
||||
; CHECK-NEXT: block1:
|
||||
; CHECK-NEXT: [[CMPA_NOT:%.*]] = xor i1 %cmpa, true
|
||||
; CHECK-NEXT: [[CMPB_NOT:%.*]] = xor i1 %cmpb, true
|
||||
; CHECK-NEXT: [[CMPA_NOT:%.*]] = xor i1 [[CMPA:%.*]], true
|
||||
; CHECK-NEXT: [[CMPB_NOT:%.*]] = xor i1 [[CMPB:%.*]], true
|
||||
; CHECK-NEXT: [[BRMERGE:%.*]] = or i1 [[CMPA_NOT]], [[CMPB_NOT]]
|
||||
; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[CMPA_NOT]], i32 0, i32 2, !prof !15
|
||||
; CHECK-NEXT: [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof !16
|
||||
|
|
@ -466,8 +614,8 @@ exit:
|
|||
define i32 @SimplifyCondBranchToCondBranchSwapMissingWeight(i1 %cmpa, i1 %cmpb) {
|
||||
; CHECK-LABEL: @SimplifyCondBranchToCondBranchSwapMissingWeight(
|
||||
; CHECK-NEXT: block1:
|
||||
; CHECK-NEXT: [[CMPA_NOT:%.*]] = xor i1 %cmpa, true
|
||||
; CHECK-NEXT: [[CMPB_NOT:%.*]] = xor i1 %cmpb, true
|
||||
; CHECK-NEXT: [[CMPA_NOT:%.*]] = xor i1 [[CMPA:%.*]], true
|
||||
; CHECK-NEXT: [[CMPB_NOT:%.*]] = xor i1 [[CMPB:%.*]], true
|
||||
; CHECK-NEXT: [[BRMERGE:%.*]] = or i1 [[CMPA_NOT]], [[CMPB_NOT]]
|
||||
; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[CMPA_NOT]], i32 0, i32 2, !prof !17
|
||||
; CHECK-NEXT: [[OUTVAL:%.*]] = select i1 [[BRMERGE]], i32 [[DOTMUX]], i32 1, !prof !18
|
||||
|
|
|
|||
Loading…
Reference in New Issue