forked from OSchip/llvm-project
[ARC] Add more load/store variants.
On ARC ISA, general format of load instruction is this:
LD<zz><.x><.aa><.di> a, [b,c]
And general format of store is this:
ST<zz><.aa><.di> c, [b,s9]
Where:
<zz> is data size field and can be one of
<empty> (bits 00) - Word (32-bit), default behavior
B (bits 01) - Byte
H (bits 10) - Half-word (16-bit)
<.x> is data extend mode:
<empty> (bit 0) - If size is not Word(32-bit), then data is zero extended
X (bit 1) - If size is not Word(32-bit), then data is sign extended
<.aa> is address write-back mode:
<empty> (bits 00) - no write-back
.AW (bits 01) - Preincrement, base register updated pre memory transaction
.AB (bits 10) - Postincrement, base register updated post memory transaction
<.di> is cache bypass mode:
<empty> (bit 0) - Cached memory access, default mode
.DI (bit 1) - Non-cached data memory access
This patch adds these load/store instruction variants to the ARC backend.
Patch By Denis Antrushin! <denis@synopsys.com>
Differential Revision: https://reviews.llvm.org/D58980
llvm-svn: 356200
This commit is contained in:
Pete Couperus
parent
51fe000d8a
commit
9fd1848823
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@ -55,6 +55,44 @@ def GPR32Reduced : Operand<iAny> {
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let DecoderMethod = "DecodeGBR32ShortRegister";
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}
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// Helper classes for load/store instructions
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class DataSizeMode<bits<2> mode, string instSfx, string asmSfx> {
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bits<2> Value = mode;
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string InstSuffix = instSfx;
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string AsmSuffix = asmSfx;
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}
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class ExtMode<bit mode, string instSfx, string asmSfx> {
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bit Value = mode;
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string InstSuffix = instSfx;
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string AsmSuffix = asmSfx;
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}
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class AddrMode<bits<2> mode, string instSfx, string asmSfx> {
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bits<2> Value = mode;
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string InstSuffix = instSfx;
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string AsmSuffix = asmSfx;
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}
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class CacheMode<bit mode, string instSfx, string asmSfx> {
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bit Value = mode;
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string InstSuffix = instSfx;
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string AsmSuffix = asmSfx;
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}
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def ByteSM : DataSizeMode<0b01, "B", "b">;
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def HalfSM : DataSizeMode<0b10, "H", "h">;
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def WordSM : DataSizeMode<0b00, "", "">;
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def NoEM : ExtMode<0, "", "">;
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def SignedEM : ExtMode<1, "_X", ".x">;
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def NoAM : AddrMode<0b00, "", "">;
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def PreIncAM : AddrMode<0b01, "_AW", ".aw">;
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def PostIncAM : AddrMode<0b10, "_AB", ".ab">;
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def NoCC : CacheMode<0b0, "", "">;
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def UncachedCC : CacheMode<0b1, "_DI", ".di">;
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class InstARC<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
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: Instruction, Encoding64 {
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@ -64,6 +102,18 @@ class InstARC<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
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let AsmString = asmstr;
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let Pattern = pattern;
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let Size = sz;
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// Load/Store instruction properties
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DataSizeMode ZZ = WordSM;
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ExtMode X = NoEM;
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AddrMode AA = NoAM;
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CacheMode DI = NoCC;
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// Field used for relation models
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string BaseOpcode = "";
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//TSFlags
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let TSFlags{1-0} = AA.Value;
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}
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// ARC pseudo instructions format
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@ -354,6 +404,8 @@ class F32_LD_RS9<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
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let Inst{8-7} = zz;
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let Inst{6} = x;
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let Inst{5-0} = A;
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let BaseOpcode = "ld_rs9";
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}
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class F32_LD_ADDR<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
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@ -363,6 +415,8 @@ class F32_LD_ADDR<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
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let B = addr{14-9};
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let S9 = addr{8-0};
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let BaseOpcode = "ld_rs9";
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}
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@ -387,6 +441,8 @@ class F32_LD_LIMM<bit x, bit di, bits<2> zz, dag outs, dag ins,
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let Inst{6} = x;
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let Inst{5-0} = A;
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let DecoderMethod = "DecodeLdLImmInstruction";
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let BaseOpcode = "ld_limm";
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}
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// Register + LImm load. The 32-bit immediate address is in Inst[63-32].
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@ -415,6 +471,8 @@ class F32_LD_RLIMM<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
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let Inst{11-6} = LImmReg;
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let Inst{5-0} = A;
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let DecoderMethod = "DecodeLdRLImmInstruction";
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let BaseOpcode = "ld_rlimm";
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}
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// Register + S9 Store. (B + S9)
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@ -437,6 +495,8 @@ class F32_ST_RS9<bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
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let Inst{4-3} = aa;
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let Inst{2-1} = zz;
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let Inst{0} = 0;
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let BaseOpcode = "st_rs9";
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}
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class F32_ST_ADDR<bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
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@ -446,6 +506,8 @@ class F32_ST_ADDR<bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
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let B = addr{14-9};
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let S9 = addr{8-0};
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let BaseOpcode = "st_rs9";
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}
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// LImm Store.
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@ -469,6 +531,8 @@ class F32_ST_LIMM<bit di, bits<2> zz, dag outs, dag ins,
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let Inst{2-1} = zz;
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let Inst{0} = 0;
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let DecoderMethod = "DecodeStLImmInstruction";
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let BaseOpcode = "st_limm";
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}
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// Compact Move/Load.
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@ -27,6 +27,19 @@ using namespace llvm;
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#include "ARCGenInstrInfo.inc"
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#define DEBUG_TYPE "arc-inst-info"
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enum AddrIncType {
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NoAddInc = 0,
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PreInc = 1,
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PostInc = 2,
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Scaled = 3
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};
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enum TSFlagsConstants {
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TSF_AddrModeOff = 0,
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TSF_AddModeMask = 3
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};
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// Pin the vtable to this file.
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void ARCInstrInfo::anchor() {}
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@ -395,3 +408,35 @@ unsigned ARCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
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}
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return MI.getDesc().getSize();
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}
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bool ARCInstrInfo::isPostIncrement(const MachineInstr &MI) const {
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const MCInstrDesc &MID = MI.getDesc();
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const uint64_t F = MID.TSFlags;
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return ((F >> TSF_AddrModeOff) & TSF_AddModeMask) == PostInc;
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}
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bool ARCInstrInfo::isPreIncrement(const MachineInstr &MI) const {
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const MCInstrDesc &MID = MI.getDesc();
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const uint64_t F = MID.TSFlags;
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return ((F >> TSF_AddrModeOff) & TSF_AddModeMask) == PreInc;
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}
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bool ARCInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
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unsigned &BasePos,
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unsigned &OffsetPos) const {
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if (!MI.mayLoad() && !MI.mayStore())
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return false;
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BasePos = 1;
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OffsetPos = 2;
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if (isPostIncrement(MI) || isPreIncrement(MI)) {
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BasePos++;
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OffsetPos++;
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}
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if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
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return false;
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return true;
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}
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@ -81,6 +81,16 @@ public:
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool isPostIncrement(const MachineInstr &MI) const override;
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// ARC-specific
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bool isPreIncrement(const MachineInstr &MI) const;
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virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
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unsigned &BasePos,
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unsigned &OffsetPos) const override;
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// Emit code before MBBI to load immediate value into physical register Reg.
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// Returns an iterator to the new instruction.
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MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB,
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@ -787,50 +787,47 @@ let isReturn = 1, isTerminator = 1 in {
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// Load/Store instructions.
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//----------------------------------------------------------------------------
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// Filter class for load/store mappings
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class ArcLdStRel;
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// Load instruction variants:
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// Control bits: x, aa, di, zz
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// x - sign extend.
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// aa - incrementing mode. (N/A for LIMM).
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// di - uncached.
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// zz - data size.
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multiclass ArcLdInst<bits<2> zz, string asmop> {
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let mayLoad = 1 in {
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def _rs9 : F32_LD_ADDR<0, 0b00, 0, zz,
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(outs GPR32:$A), (ins MEMrs9:$addr),
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!strconcat(asmop, "\t$A, [$addr]"), []>;
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multiclass ArcLdInst<DataSizeMode zz, ExtMode x, CacheMode di, string asmop> {
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let mayLoad = 1, ZZ = zz, X = x, DI = di in {
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def _rs9: F32_LD_ADDR<x.Value, NoAM.Value, di.Value, zz.Value,
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(outs GPR32:$A), (ins MEMrs9:$addr),
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!strconcat(asmop, "\t$A, [$addr]"), []>, ArcLdStRel;
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def _limm : F32_LD_LIMM<0, 0, zz,
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(outs GPR32:$A), (ins MEMii:$addr),
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!strconcat(asmop, "\t$A, [$addr]"), []>;
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def _limm: F32_LD_LIMM<x.Value, di.Value, zz.Value,
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(outs GPR32:$A), (ins MEMii:$addr),
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!strconcat(asmop, "\t$A, [$addr]"), []>, ArcLdStRel;
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def _rlimm : F32_LD_RLIMM<0, 0b00, 0, zz,
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(outs GPR32:$A), (ins MEMrlimm:$addr),
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!strconcat(asmop, "\t$A, [$addr]"), []>;
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def _rlimm: F32_LD_RLIMM<x.Value, NoAM.Value, di.Value, zz.Value,
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(outs GPR32:$A), (ins MEMrlimm:$addr),
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!strconcat(asmop, "\t$A, [$addr]"), []>, ArcLdStRel;
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def _X_rs9 : F32_LD_ADDR<1, 0b00, 0, zz,
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(outs GPR32:$A), (ins MEMrs9:$addr),
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!strconcat(asmop, ".x\t$A, [$addr]"), []>;
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def _X_limm : F32_LD_LIMM<1, 0, zz,
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(outs GPR32:$A), (ins MEMii:$addr),
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!strconcat(asmop, ".x\t$A, [$addr]"), []>;
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def _X_rlimm : F32_LD_RLIMM<1, 0b00, 0, zz,
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(outs GPR32:$A), (ins MEMrlimm:$addr),
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!strconcat(asmop, ".x\t$A, [$addr]"), []>;
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def _AB_rs9 : F32_LD_RS9<0, 0b10, 0, zz,
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(outs GPR32:$addrout, GPR32:$A),
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(ins GPR32:$B, immS<9>:$S9),
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!strconcat(asmop, ".ab\t$A, [$B,$S9]"), []>
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{ let Constraints = "$addrout = $B"; }
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foreach aa = [PreIncAM, PostIncAM] in {
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def aa.InstSuffix#_rs9: F32_LD_RS9<x.Value, aa.Value, di.Value, zz.Value,
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(outs GPR32:$A, GPR32:$addrout),
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(ins GPR32:$B, immS<9>:$S9),
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asmop#aa.AsmSuffix#"\t$A, [$B,$S9]", []>, ArcLdStRel
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{ let Constraints = "$addrout = $B"; let AA = aa; }
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}
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}
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}
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foreach di = [NoCC, UncachedCC] in {
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defm LD#di.InstSuffix : ArcLdInst<WordSM, NoEM, di, "ld"#di.AsmSuffix>;
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foreach zz = [ByteSM, HalfSM] in {
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foreach x = [NoEM, SignedEM] in {
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defm LD#zz.InstSuffix#x.InstSuffix#di.InstSuffix : ArcLdInst<zz, x, di, "ld"#zz.AsmSuffix#x.AsmSuffix#di.AsmSuffix>;
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}
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}
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}
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// Load instruction definitions.
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defm LD : ArcLdInst<0b00, "ld">;
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defm LDH : ArcLdInst<0b10, "ldh">;
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defm LDB : ArcLdInst<0b01, "ldb">;
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// Load instruction patterns.
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// 32-bit loads.
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@ -872,25 +869,32 @@ def : Pat<(sextloadi8 AddrModeS9:$addr),(LDB_X_rs9 AddrModeS9:$addr)>;
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// aa - incrementing mode. (N/A for LIMM).
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// di - uncached.
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// zz - data size.
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multiclass ArcStInst<bits<2> zz, string asmop> {
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let mayStore = 1 in {
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def _rs9 : F32_ST_ADDR<0b00, 0, zz, (outs), (ins GPR32:$C, MEMrs9:$addr),
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!strconcat(asmop, "\t$C, [$addr]"), []>;
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multiclass ArcStInst<DataSizeMode zz, CacheMode di, string asmop> {
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let mayStore = 1, ZZ = zz, DI = di in {
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def _rs9: F32_ST_ADDR<NoAM.Value, di.Value, zz.Value,
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(outs), (ins GPR32:$C, MEMrs9:$addr),
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!strconcat(asmop, "\t$C, [$addr]"), []>, ArcLdStRel;
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def _limm : F32_ST_LIMM<0, zz, (outs), (ins GPR32:$C, MEMii:$addr),
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!strconcat(asmop, "\t$C, [$addr]"), []>;
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def _limm: F32_ST_LIMM<di.Value, zz.Value,
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(outs), (ins GPR32:$C, MEMii:$addr),
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!strconcat(asmop, "\t$C, [$addr]"), []>, ArcLdStRel;
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def _AW_rs9 : F32_ST_RS9<0b01, 0, zz, (outs GPR32:$addrout),
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(ins GPR32:$C, GPR32:$B, immS<9>:$S9),
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!strconcat(asmop, ".aw\t$C, [$B,$S9]"), []>
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{ let Constraints = "$addrout = $B"; }
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foreach aa = [PreIncAM, PostIncAM] in {
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def aa.InstSuffix#_rs9: F32_ST_RS9<aa.Value, di.Value, zz.Value,
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(outs GPR32:$addrout),
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(ins GPR32:$C, GPR32:$B, immS<9>:$S9),
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asmop#aa.AsmSuffix#"\t$C, [$B,$S9]", []>, ArcLdStRel
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{ let Constraints = "$addrout = $B"; let AA = aa; }
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}
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}
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}
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// Store instruction definitions.
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defm ST : ArcStInst<0b00, "st">;
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defm STH : ArcStInst<0b10, "sth">;
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defm STB : ArcStInst<0b01, "stb">;
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foreach di = [NoCC, UncachedCC] in {
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foreach zz = [ByteSM, HalfSM, WordSM] in {
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defm ST#zz.InstSuffix#di.InstSuffix : ArcStInst<zz, di, "st"#zz.AsmSuffix#di.AsmSuffix>;
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}
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}
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// Store instruction patterns.
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// 32-bit stores
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@ -911,3 +915,10 @@ def : Pat<(truncstorei8 i32:$C, AddrModeS9:$addr),
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def : Pat<(truncstorei8 i32:$C, AddrModeImm:$addr),
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(STB_limm i32:$C, AddrModeImm:$addr)>;
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def getPostIncOpcode : InstrMapping {
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let FilterClass = "ArcLdStRel";
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let RowFields = [ "BaseOpcode", "ZZ", "DI", "X"];
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let ColFields = [ "AA" ];
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let KeyCol = [ "NoAM" ];
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let ValueCols = [["PostIncAM"]];
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}
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@ -45,3 +45,50 @@
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# CHECK: st %r7, [63920]
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0x00 0x1e 0xc0 0x71 0x00 0x00 0xb0 0xf9
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# CHECK: ldb.ab %r1, [%r0,1]
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0x01 0x10 0x81 0x04
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# CHECK: stb.ab %r2, [%r0,1]
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0x01 0x18 0x92 0x00
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# CHECK: ldh.ab %r3, [%r0,12]
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0x0C 0x10 0x03 0x05
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# CHECK: sth.ab %r4, [%r0,18]
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0x12 0x18 0x14 0x01
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# CHECK: ld.ab %r5, [%r2,128]
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0x80 0x12 0x05 0x04
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# CHECK: st.ab %r6, [%r2,64]
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0x40 0x1A 0x90 0x01
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# CHECK: ldb.aw %r7, [%r0,1]
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0x01 0x10 0x87 0x02
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# CHECK: stb.aw %r8, [%r0,1]
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0x01 0x18 0x0A 0x02
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# CHECK: ldh.aw %r3, [%r0,12]
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0x0C 0x10 0x03 0x03
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# CHECK: sth.aw %r3, [%r0,18]
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0x12 0x18 0xCC 0x00
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# CHECK: ld.aw %r6, [%r2,128]
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0x80 0x12 0x06 0x02
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# CHECK: st.aw %r6, [%r2,64]
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0x40 0x1A 0x88 0x01
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# CHECK: ld.aw %r6, [%r2,128]
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0x80 0x12 0x06 0x02
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# CHECK: st.aw %r6, [%r2,64]
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0x40 0x1A 0x88 0x01
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# CHECK: ldb.x.di.aw %r0, [%r8,8]
|
||||
0x08 0x10 0xC0 0x1A
|
||||
|
||||
# CHECK: stb.di.ab %r0, [%r9,64]
|
||||
0x40 0x19 0x32 0x10
|
||||
|
|
|
|||
Loading…
Reference in New Issue