forked from OSchip/llvm-project
[ARM] Add tests for D34515
This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
This commit is contained in:
Roger Ferrer Ibanez
parent
746f152dd6
commit
9fcc4727ac
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@ -1,20 +1,27 @@
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; RUN: llc -mtriple=arm-eabi < %s | FileCheck %s
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define i1 @t1(i64 %x) {
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; CHECK-LABEL: t1:
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; CHECK: lsr r0, r1, #31
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%B = icmp slt i64 %x, 0
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ret i1 %B
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}
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define i1 @t2(i64 %x) {
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; CHECK-LABEL: t2:
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; CHECK: mov r0, #0
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; CHECK: cmp r1, #0
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; CHECK: moveq r0, #1
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%tmp = icmp ult i64 %x, 4294967296
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ret i1 %tmp
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}
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define i1 @t3(i32 %x) {
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; CHECK-LABEL: t3:
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; CHECK: mov r0, #0
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%tmp = icmp ugt i32 %x, -1
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ret i1 %tmp
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}
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; CHECK: cmp
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; CHECK-NOT: cmp
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@ -3,9 +3,15 @@
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; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \
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; RUN: | FileCheck %s --check-prefix=ARMT2
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; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 %s -o - \
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; RUN: | FileCheck %s --check-prefix=THUMB1
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; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \
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; RUN: | FileCheck %s --check-prefix=THUMB2
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; RUN: llc -mtriple=thumbv8m.base-eabi %s -o - \
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; RUN: | FileCheck %s --check-prefix=V8MBASE
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define i32 @t1(i32 %c) nounwind readnone {
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entry:
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; ARM-LABEL: t1:
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@ -17,6 +23,14 @@ entry:
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; ARMT2: movw [[R:r[0-1]]], #357
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; ARMT2: movwgt [[R]], #123
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; THUMB1-LABEL: t1:
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; THUMB1: mov r1, r0
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; THUMB1: movs r2, #255
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; THUMB1: adds r2, #102
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; THUMB1: movs r0, #123
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; THUMB1: cmp r1, #1
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; THUMB1: bgt
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; THUMB2-LABEL: t1:
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; THUMB2: movw [[R:r[0-1]]], #357
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; THUMB2: movgt [[R]], #123
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@ -37,6 +51,10 @@ entry:
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; ARMT2: mov [[R:r[0-1]]], #123
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; ARMT2: movwgt [[R]], #357
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; THUMB1-LABEL: t2:
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; THUMB1: cmp r{{[0-9]+}}, #1
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; THUMB1: bgt
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; THUMB2-LABEL: t2:
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; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #123
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; THUMB2: movwgt [[R]], #357
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@ -56,6 +74,13 @@ entry:
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; ARMT2: mov [[R:r[0-1]]], #0
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; ARMT2: movweq [[R]], #1
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; THUMB1-LABEL: t3:
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; THUMB1: mov r1, r0
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; THUMB1: movs r0, #1
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; THUMB1: movs r2, #0
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; THUMB1: cmp r1, #160
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; THUMB1: beq
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; THUMB2-LABEL: t3:
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; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #0
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; THUMB2: moveq [[R]], #1
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@ -74,6 +99,10 @@ entry:
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; ARMT2: movwlt [[R0:r[0-9]+]], #65365
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; ARMT2: movtlt [[R0]], #65365
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; THUMB1-LABEL: t4:
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; THUMB1: cmp r{{[0-9]+}}, r{{[0-9]+}}
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; THUMB1: b{{lt|ge}}
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; THUMB2-LABEL: t4:
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; THUMB2: mvnlt [[R0:r[0-9]+]], #11141290
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%0 = icmp slt i32 %a, %b
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@ -90,6 +119,12 @@ entry:
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; ARM-NOT: mov
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; ARM: movne r0, #0
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; THUMB1-LABEL: t5:
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; THUMB1: mov r1, r0
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; THUMB1: movs r0, #0
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; THUMB1: cmp r1, #1
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; THUMB1: bne
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; THUMB2-LABEL: t5:
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; THUMB2-NOT: mov
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; THUMB2: cmp r0, #1
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@ -107,6 +142,10 @@ entry:
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; ARM: cmp r0, #0
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; ARM: movne r0, #1
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; THUMB1-LABEL: t6:
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; THUMB1: cmp r{{[0-9]+}}, #0
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; THUMB1: bne
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; THUMB2-LABEL: t6:
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; THUMB2-NOT: mov
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; THUMB2: cmp r0, #0
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@ -116,3 +155,202 @@ entry:
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%lnot.ext = zext i1 %tobool to i32
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ret i32 %lnot.ext
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}
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define i32 @t7(i32 %a, i32 %b) nounwind readnone {
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entry:
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; ARM-LABEL: t7:
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; ARM: mov r2, #0
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; ARM: cmp r0, r1
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; ARM: movne r2, #1
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; ARM: lsl r0, r2, #2
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; ARMT2-LABEL: t7:
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; ARMT2: mov r2, #0
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; ARMT2: cmp r0, r1
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; ARMT2: movwne r2, #1
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; ARMT2: lsl r0, r2, #2
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; THUMB1-LABEL: t7:
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; THUMB1: movs r2, #1
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; THUMB1: movs r3, #0
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; THUMB1: cmp r0, r1
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; THUMB1: bne .LBB6_2
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; THUMB1: mov r2, r3
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; THUMB1: .LBB6_2:
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; THUMB1: lsls r0, r2, #2
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; THUMB2-LABEL: t7:
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; THUMB2: movs r2, #0
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; THUMB2: cmp r0, r1
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; THUMB2: it ne
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; THUMB2: movne r2, #1
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; THUMB2: lsls r0, r2, #2
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%0 = icmp ne i32 %a, %b
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%1 = select i1 %0, i32 4, i32 0
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ret i32 %1
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}
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define void @t8(i32 %a) {
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entry:
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; ARM scheduler emits icmp/zext before both calls, so isn't relevant
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; ARMT2-LABEL: t8:
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; ARMT2: mov r1, r0
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; ARMT2: mov r0, #9
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; ARMT2: mov r4, #0
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; ARMT2: cmp r1, #5
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; ARMT2: movweq r4, #1
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; ARMT2: bl t7
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; THUMB1-LABEL: t8:
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; THUMB1: mov r1, r0
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; THUMB1: movs r4, #1
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; THUMB1: movs r0, #0
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; THUMB1: cmp r1, #5
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; THUMB1: beq .LBB7_2
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; THUMB1: mov r4, r0
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; THUMB2-LABEL: t8:
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; THUMB2: mov r1, r0
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; THUMB2: movs r4, #0
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; THUMB2: cmp r1, #5
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; THUMB2: it eq
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; THUMB2: moveq r4, #1
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%cmp = icmp eq i32 %a, 5
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%conv = zext i1 %cmp to i32
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%call = tail call i32 @t7(i32 9, i32 %a)
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tail call i32 @t7(i32 %conv, i32 %call)
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ret void
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}
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define void @t9(i8* %a, i8 %b) {
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entry:
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; ARM scheduler emits icmp/zext before both calls, so isn't relevant
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; ARMT2-LABEL: t9:
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; ARMT2: cmp r4, r4
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; ARMT2: movweq r0, #1
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; THUMB1-LABEL: t9:
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; THUMB1: cmp r4, r4
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; THUMB1: beq .LBB8_2
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; THUMB1: mov r0, r1
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; THUMB2-LABEL: t9:
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; THUMB2: cmp r4, r4
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; THUMB2: it eq
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; THUMB2: moveq r0, #1
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%0 = load i8, i8* %a
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%conv = sext i8 %0 to i32
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%conv119 = zext i8 %0 to i32
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%conv522 = and i32 %conv, 255
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%cmp723 = icmp eq i32 %conv522, %conv119
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tail call void @f(i1 zeroext %cmp723)
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br i1 %cmp723, label %while.body, label %while.end
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while.body: ; preds = %entry, %while.body
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%ref.025 = phi i8 [ %inc9, %while.body ], [ %0, %entry ]
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%in.024 = phi i32 [ %inc, %while.body ], [ %conv, %entry ]
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%inc = add i32 %in.024, 1
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%inc9 = add i8 %ref.025, 1
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%conv1 = zext i8 %inc9 to i32
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%cmp = icmp slt i32 %conv1, %conv119
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%conv5 = and i32 %inc, 255
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br i1 %cmp, label %while.body, label %while.end
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while.end:
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ret void
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}
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declare void @f(i1 zeroext)
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define i1 @t10() {
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entry:
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%q = alloca i32
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%p = alloca i32
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store i32 -3, i32* %q
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store i32 -8, i32* %p
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%0 = load i32, i32* %q
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%1 = load i32, i32* %p
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%div = sdiv i32 %0, %1
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%mul = mul nsw i32 %div, %1
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%rem = srem i32 %0, %1
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%add = add nsw i32 %mul, %rem
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%cmp = icmp eq i32 %add, %0
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ret i1 %cmp
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; ARM-LABEL: t10:
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; ARM: mov r0, #0
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; ARM: cmn r1, #3
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; ARM: moveq r0, #1
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; ARMT2-LABEL: t10:
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; ARMT2: mov r0, #0
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; ARMT2: cmn r1, #3
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; ARMT2: movweq r0, #1
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; THUMB1-LABEL: t10:
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; THUMB1: movs r0, #1
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; THUMB1: movs r1, #0
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; THUMB1: cmp r2, r5
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; THUMB1: beq .LBB9_2
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; THUMB1: mov r0, r1
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; THUMB2-LABEL: t10:
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; THUMB2: adds r0, #3
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; THUMB2: mov.w r0, #0
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; THUMB2: it eq
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; THUMB2: moveq r0, #1
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; V8MBASE-LABEL: t10:
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; V8MBASE-NOT: movs r0, #0
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; V8MBASE: movs r0, #7
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}
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define i1 @t11() {
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entry:
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%bit = alloca i32
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%load = load i32, i32* %bit
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%clear = and i32 %load, -4096
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%set = or i32 %clear, 33
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store i32 %set, i32* %bit
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%load1 = load i32, i32* %bit
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%clear2 = and i32 %load1, -33550337
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%set3 = or i32 %clear2, 40960
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%clear5 = and i32 %set3, 4095
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%rem = srem i32 %clear5, 10
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%clear9 = and i32 %set3, -4096
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%set10 = or i32 %clear9, %rem
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store i32 %set10, i32* %bit
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%clear12 = and i32 %set10, 4095
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%cmp = icmp eq i32 %clear12, 3
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ret i1 %cmp
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; ARM-LABEL: t11:
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; ARM: mov r0, #0
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; ARM: cmp r1, #3
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; ARM: moveq r0, #1
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; ARMT2-LABEL: t11:
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; ARMT2: mov r0, #0
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; ARMT2: cmp r1, #3
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; ARMT2: movweq r0, #1
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; THUMB1-LABEL: t11:
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; THUMB1-NOT: movs r0, #0
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; THUMB1: movs r0, #5
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; THUMB2-LABEL: t11:
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; THUMB2: movs r0, #0
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; THUMB2: cmp r1, #3
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; THUMB2: it eq
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; THUMB2: moveq r0, #1
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; V8MBASE-LABEL: t11:
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; V8MBASE-NOT: movs r0, #0
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; V8MBASE: movw r0, #40960
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}
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@ -0,0 +1,149 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 %s -verify-machineinstrs -o - | FileCheck %s
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define i32 @test1a(i32 %a, i32 %b) {
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; CHECK-LABEL: test1a:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: movs r0, #1
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: bne .LBB0_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: .LBB0_2: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp ne i32 %a, %b
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%cond = zext i1 %cmp to i32
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ret i32 %cond
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}
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define i32 @test1b(i32 %a, i32 %b) {
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; CHECK-LABEL: test1b:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: movs r0, #1
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: beq .LBB1_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: .LBB1_2: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp eq i32 %a, %b
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%cond = zext i1 %cmp to i32
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ret i32 %cond
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}
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define i32 @test2a(i32 %a, i32 %b) {
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; CHECK-LABEL: test2a:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: movs r0, #1
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: beq .LBB2_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: .LBB2_2: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp eq i32 %a, %b
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%cond = zext i1 %cmp to i32
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ret i32 %cond
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}
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define i32 @test2b(i32 %a, i32 %b) {
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; CHECK-LABEL: test2b:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: movs r0, #1
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; CHECK-NEXT: movs r3, #0
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: bne .LBB3_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: .LBB3_2: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp ne i32 %a, %b
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%cond = zext i1 %cmp to i32
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ret i32 %cond
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}
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define i32 @test3a(i32 %a, i32 %b) {
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; CHECK-LABEL: test3a:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: movs r3, #4
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: beq .LBB4_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: .LBB4_2: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%cmp = icmp eq i32 %a, %b
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%cond = select i1 %cmp, i32 0, i32 4
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ret i32 %cond
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}
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define i32 @test3b(i32 %a, i32 %b) {
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; CHECK-LABEL: test3b:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #1
|
||||
; CHECK-NEXT: movs r3, #0
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: beq .LBB5_2
|
||||
; CHECK-NEXT: @ %bb.1: @ %entry
|
||||
; CHECK-NEXT: mov r2, r3
|
||||
; CHECK-NEXT: .LBB5_2: @ %entry
|
||||
; CHECK-NEXT: lsls r0, r2, #2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%cmp = icmp eq i32 %a, %b
|
||||
%cond = select i1 %cmp, i32 4, i32 0
|
||||
ret i32 %cond
|
||||
}
|
||||
|
||||
; FIXME: This one hasn't changed actually
|
||||
; but could look like test3b
|
||||
define i32 @test4a(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: test4a:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: mov r2, r0
|
||||
; CHECK-NEXT: movs r0, #0
|
||||
; CHECK-NEXT: movs r3, #4
|
||||
; CHECK-NEXT: cmp r2, r1
|
||||
; CHECK-NEXT: bne .LBB6_2
|
||||
; CHECK-NEXT: @ %bb.1: @ %entry
|
||||
; CHECK-NEXT: mov r0, r3
|
||||
; CHECK-NEXT: .LBB6_2: @ %entry
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%cmp = icmp ne i32 %a, %b
|
||||
%cond = select i1 %cmp, i32 0, i32 4
|
||||
ret i32 %cond
|
||||
}
|
||||
|
||||
define i32 @test4b(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: test4b:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: movs r2, #1
|
||||
; CHECK-NEXT: movs r3, #0
|
||||
; CHECK-NEXT: cmp r0, r1
|
||||
; CHECK-NEXT: bne .LBB7_2
|
||||
; CHECK-NEXT: @ %bb.1: @ %entry
|
||||
; CHECK-NEXT: mov r2, r3
|
||||
; CHECK-NEXT: .LBB7_2: @ %entry
|
||||
; CHECK-NEXT: lsls r0, r2, #2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%cmp = icmp ne i32 %a, %b
|
||||
%cond = select i1 %cmp, i32 4, i32 0
|
||||
ret i32 %cond
|
||||
}
|
||||
|
||||
|
|
@ -1,22 +1,28 @@
|
|||
; RUN: llc -mtriple=thumb-eabi < %s | FileCheck %s
|
||||
|
||||
define i1 @t1(i64 %x) {
|
||||
%B = icmp slt i64 %x, 0
|
||||
ret i1 %B
|
||||
; CHECK-LABEL: t1:
|
||||
; CHECK: lsrs r0, r1, #31
|
||||
%B = icmp slt i64 %x, 0
|
||||
ret i1 %B
|
||||
}
|
||||
|
||||
define i1 @t2(i64 %x) {
|
||||
%tmp = icmp ult i64 %x, 4294967296
|
||||
ret i1 %tmp
|
||||
; CHECK-LABEL: t2:
|
||||
; CHECK: movs r0, #1
|
||||
; CHECK: movs r2, #0
|
||||
; CHECK: cmp r1, #0
|
||||
; CHECK: beq .LBB1_2
|
||||
%tmp = icmp ult i64 %x, 4294967296
|
||||
ret i1 %tmp
|
||||
}
|
||||
|
||||
define i1 @t3(i32 %x) {
|
||||
%tmp = icmp ugt i32 %x, -1
|
||||
ret i1 %tmp
|
||||
; CHECK-LABEL: t3:
|
||||
; CHECK: movs r0, #0
|
||||
%tmp = icmp ugt i32 %x, -1
|
||||
ret i1 %tmp
|
||||
}
|
||||
|
||||
; CHECK: cmp
|
||||
|
||||
; CHECK-NOT: cmp
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue