From 9fab370d79eb8c09bff29a8c0744060a15d63607 Mon Sep 17 00:00:00 2001
From: Alex Lorenz <arphaman@gmail.com>
Date: Tue, 14 Jul 2015 21:24:41 +0000
Subject: [PATCH] MIR Serialization: Serialize the machine basic block live in
 registers.

llvm-svn: 242204
---
 llvm/include/llvm/CodeGen/MIRYamlMapping.h    |  5 ++--
 llvm/lib/CodeGen/MIRParser/MIParser.cpp       | 21 ++++++++++++++++
 llvm/lib/CodeGen/MIRParser/MIParser.h         |  6 +++++
 llvm/lib/CodeGen/MIRParser/MIRParser.cpp      |  8 ++++++
 llvm/lib/CodeGen/MIRPrinter.cpp               | 10 +++++++-
 .../CodeGen/MIR/X86/basic-block-liveins.mir   | 25 +++++++++++++++++++
 .../X86/expected-named-register-livein.mir    | 21 ++++++++++++++++
 7 files changed, 93 insertions(+), 3 deletions(-)
 create mode 100644 llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir
 create mode 100644 llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir

diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
index 2ecd445f0deb..9798e5cef645 100644
--- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
@@ -102,9 +102,9 @@ struct MachineBasicBlock {
   unsigned Alignment = 0;
   bool IsLandingPad = false;
   bool AddressTaken = false;
-  // TODO: Serialize the successor weights and liveins.
+  // TODO: Serialize the successor weights.
   std::vector<FlowStringValue> Successors;
-
+  std::vector<FlowStringValue> LiveIns;
   std::vector<StringValue> Instructions;
 };
 
@@ -117,6 +117,7 @@ template <> struct MappingTraits<MachineBasicBlock> {
     YamlIO.mapOptional("isLandingPad", MBB.IsLandingPad);
     YamlIO.mapOptional("addressTaken", MBB.AddressTaken);
     YamlIO.mapOptional("successors", MBB.Successors);
+    YamlIO.mapOptional("liveins", MBB.LiveIns);
     YamlIO.mapOptional("instructions", MBB.Instructions);
   }
 };
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index dec06bc9cc8f..c00011288a60 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -78,6 +78,7 @@ public:
 
   bool parse(MachineInstr *&MI);
   bool parseMBB(MachineBasicBlock *&MBB);
+  bool parseNamedRegister(unsigned &Reg);
 
   bool parseRegister(unsigned &Reg);
   bool parseRegisterFlag(unsigned &Flags);
@@ -215,6 +216,18 @@ bool MIParser::parseMBB(MachineBasicBlock *&MBB) {
   return false;
 }
 
+bool MIParser::parseNamedRegister(unsigned &Reg) {
+  lex();
+  if (Token.isNot(MIToken::NamedRegister))
+    return error("expected a named register");
+  if (parseRegister(Reg))
+    return 0;
+  lex();
+  if (Token.isNot(MIToken::Eof))
+    return error("expected end of string after the register reference");
+  return false;
+}
+
 static const char *printImplicitRegisterFlag(const MachineOperand &MO) {
   assert(MO.isImplicit());
   return MO.isDef() ? "implicit-def" : "implicit";
@@ -583,3 +596,11 @@ bool llvm::parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM,
                              const SlotMapping &IRSlots, SMDiagnostic &Error) {
   return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseMBB(MBB);
 }
+
+bool llvm::parseNamedRegisterReference(unsigned &Reg, SourceMgr &SM,
+                                       MachineFunction &MF, StringRef Src,
+                                       const PerFunctionMIParsingState &PFS,
+                                       const SlotMapping &IRSlots,
+                                       SMDiagnostic &Error) {
+  return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseNamedRegister(Reg);
+}
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.h b/llvm/lib/CodeGen/MIRParser/MIParser.h
index 8a911b32a764..fca4c4e6f885 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.h
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.h
@@ -40,6 +40,12 @@ bool parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM,
                        const PerFunctionMIParsingState &PFS,
                        const SlotMapping &IRSlots, SMDiagnostic &Error);
 
+bool parseNamedRegisterReference(unsigned &Reg, SourceMgr &SM,
+                                 MachineFunction &MF, StringRef Src,
+                                 const PerFunctionMIParsingState &PFS,
+                                 const SlotMapping &IRSlots,
+                                 SMDiagnostic &Error);
+
 } // end namespace llvm
 
 #endif
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index bfec6c59164f..16b0e1655891 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -321,6 +321,14 @@ bool MIRParserImpl::initializeMachineBasicBlock(
     // TODO: Report an error when adding the same successor more than once.
     MBB.addSuccessor(SuccMBB);
   }
+  // Parse the liveins.
+  for (const auto &LiveInSource : YamlMBB.LiveIns) {
+    unsigned Reg = 0;
+    if (parseNamedRegisterReference(Reg, SM, MF, LiveInSource.Value, PFS,
+                                    IRSlots, Error))
+      return error(Error, LiveInSource.SourceRange);
+    MBB.addLiveIn(Reg);
+  }
   // Parse the instructions.
   for (const auto &MISource : YamlMBB.Instructions) {
     MachineInstr *MI = nullptr;
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index ddc1d0a0cc15..d5cf9244199e 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -233,7 +233,15 @@ void MIRPrinter::convert(ModuleSlotTracker &MST,
     MIPrinter(StrOS, MST, RegisterMaskIds).printMBBReference(*SuccMBB);
     YamlMBB.Successors.push_back(StrOS.str());
   }
-
+  // Print the live in registers.
+  const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
+  assert(TRI && "Expected target register info");
+  for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
+    std::string Str;
+    raw_string_ostream StrOS(Str);
+    printReg(*I, StrOS, TRI);
+    YamlMBB.LiveIns.push_back(StrOS.str());
+  }
   // Print the machine instructions.
   YamlMBB.Instructions.reserve(MBB.size());
   std::string Str;
diff --git a/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir b/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir
new file mode 100644
index 000000000000..d749a0524422
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir
@@ -0,0 +1,25 @@
+# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses basic block liveins correctly.
+
+--- |
+
+  define i32 @test(i32 %a, i32 %b) {
+  body:
+    %c = add i32 %a, %b
+    ret i32 %c
+  }
+
+...
+---
+name:            test
+body:
+  # CHECK: name: body
+  # CHECK: liveins: [ '%edi', '%esi' ]
+  # CHECK-NEXT: instructions:
+  - id:          0
+    name:        body
+    liveins:     [ '%edi', '%esi' ]
+    instructions:
+      - '%eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _'
+      - 'RETQ %eax'
+...
diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir
new file mode 100644
index 000000000000..1fbe881c8c70
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir
@@ -0,0 +1,21 @@
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @test(i32 %a) {
+  body:
+    ret i32 %a
+  }
+
+...
+---
+name:            test
+body:
+  - id:          0
+    name:        body
+    # CHECK: [[@LINE+1]]:21: expected a named register
+    liveins:     [ '%0' ]
+    instructions:
+      - '%eax = COPY %edi'
+      - 'RETQ %eax'
+...