forked from OSchip/llvm-project
AMDGPU/GlobalISel: Fix scc->vcc copy handling
This was checking the size of the register with the value of the size, which happens to be exec. Also fix assuming VCC is 64-bit to fix wave32. Also remove some untested handling for physical registers which is skipped. This doesn't insert the V_CNDMASK_B32 if SCC is the physical copy source. I'm not sure if this should be trying to handle this special case instead of dealing with this in copyPhysReg. llvm-svn: 364761
This commit is contained in:
Matt Arsenault
parent
5dafcb9b11
commit
9f992c238a
llvm
lib/Target/AMDGPU
test/CodeGen/AMDGPU/GlobalISel
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@ -60,11 +60,7 @@ AMDGPUInstructionSelector::AMDGPUInstructionSelector(
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const char *AMDGPUInstructionSelector::getName() { return DEBUG_TYPE; }
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static bool isSCC(unsigned Reg, const MachineRegisterInfo &MRI) {
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if (Reg == AMDGPU::SCC)
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return true;
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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return false;
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assert(!TargetRegisterInfo::isPhysicalRegister(Reg));
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auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
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const TargetRegisterClass *RC =
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@ -77,6 +73,22 @@ static bool isSCC(unsigned Reg, const MachineRegisterInfo &MRI) {
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return RB->getID() == AMDGPU::SCCRegBankID;
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}
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static bool isVCC(unsigned Reg, const MachineRegisterInfo &MRI,
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const SIRegisterInfo &TRI) {
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assert(!TargetRegisterInfo::isPhysicalRegister(Reg));
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auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
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const TargetRegisterClass *RC =
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RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
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if (RC) {
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return RC == TRI.getWaveMaskRegClass() &&
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MRI.getType(Reg).getSizeInBits() == 1;
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}
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const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
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return RB->getID() == AMDGPU::VCCRegBankID;
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}
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bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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@ -88,14 +100,12 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
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const MachineOperand &Src = I.getOperand(1);
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unsigned SrcReg = Src.getReg();
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if (!TargetRegisterInfo::isPhysicalRegister(SrcReg) && isSCC(SrcReg, MRI)) {
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unsigned DstReg = TRI.getRegSizeInBits(I.getOperand(0).getReg(), MRI);
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unsigned DstSize = TRI.getRegSizeInBits(DstReg, MRI);
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unsigned DstReg = I.getOperand(0).getReg();
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// We have a copy from a 32-bit to 64-bit register. This happens
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// when we are selecting scc->vcc copies.
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if (DstSize == 64) {
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// Specially handle scc->vcc copies.
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if (isVCC(DstReg, MRI, TRI)) {
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const DebugLoc &DL = I.getDebugLoc();
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), I.getOperand(0).getReg())
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
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.addImm(0)
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.addReg(SrcReg);
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if (!MRI.getRegClassOrNull(SrcReg))
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@ -1690,8 +1690,8 @@ SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size,
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case AMDGPU::VGPRRegBankID:
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return &AMDGPU::VGPR_32RegClass;
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case AMDGPU::VCCRegBankID:
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// TODO: Check wavesize
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return &AMDGPU::SReg_64_XEXECRegClass;
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return isWave32 ?
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&AMDGPU::SReg_32_XM0_XEXECRegClass : &AMDGPU::SReg_64_XEXECRegClass;
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case AMDGPU::SGPRRegBankID:
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return &AMDGPU::SReg_32_XM0RegClass;
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case AMDGPU::SCCRegBankID:
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@ -1,5 +1,6 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -run-pass=instruction-select -verify-machineinstrs -global-isel -o - %s | FileCheck -check-prefix=WAVE32 %s
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---
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@ -11,11 +12,18 @@ regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr2_sgpr3
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; GCN-LABEL: name: copy
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; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
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; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[COPY]]
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: FLAT_STORE_DWORD [[COPY1]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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; WAVE64-LABEL: name: copy
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; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
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; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[COPY]]
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; WAVE64: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; WAVE64: FLAT_STORE_DWORD [[COPY1]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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; WAVE32-LABEL: name: copy
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
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; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[COPY]]
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; WAVE32: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; WAVE32: FLAT_STORE_DWORD [[COPY1]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%0:sgpr(p1) = COPY $sgpr2_sgpr3
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%1:vgpr(p1) = COPY %0
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%2:vgpr(s32) = G_IMPLICIT_DEF
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@ -23,21 +31,31 @@ body: |
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...
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---
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name: copy_vcc_scc
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name: copy_vcc_bank_scc_bank
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $scc
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; GCN-LABEL: name: copy_vcc_scc
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
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; GCN: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
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; GCN: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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; WAVE64-LABEL: name: copy_vcc_bank_scc_bank
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; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
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; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
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; WAVE64: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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; WAVE32-LABEL: name: copy_vcc_bank_scc_bank
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; WAVE32: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
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; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
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; WAVE32: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%0:vgpr(p1) = COPY $vgpr0_vgpr1
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%1:vgpr(s32) = COPY $vgpr2
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%2:vgpr(s32) = COPY $vgpr3
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@ -48,23 +66,35 @@ body: |
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...
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---
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name: copy_vcc_scc_2_uses
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name: copy_vcc_bank_scc_bank_2_uses
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $scc
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; GCN-LABEL: name: copy_vcc_scc_2_uses
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
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; GCN: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
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; GCN: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
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; GCN: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_1]], implicit $exec
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; GCN: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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; WAVE64-LABEL: name: copy_vcc_bank_scc_bank_2_uses
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; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
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; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
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; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
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; WAVE64: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_1]], implicit $exec
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; WAVE64: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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; WAVE32-LABEL: name: copy_vcc_bank_scc_bank_2_uses
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; WAVE32: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
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; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
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; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
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; WAVE32: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_1]], implicit $exec
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; WAVE32: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%0:vgpr(p1) = COPY $vgpr0_vgpr1
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%1:vgpr(s32) = COPY $vgpr2
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%2:vgpr(s32) = COPY $vgpr3
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@ -75,4 +105,36 @@ body: |
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%7:vgpr(s32) = G_SELECT %6, %1, %5
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G_STORE %7, %0 :: (store 4, addrspace 1)
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...
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---
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name: copy_vcc_bank_scc_physreg
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $scc
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; WAVE64-LABEL: name: copy_vcc_bank_scc_physreg
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; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; WAVE64: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY $scc
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; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[COPY3]], implicit $exec
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; WAVE64: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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; WAVE32-LABEL: name: copy_vcc_bank_scc_physreg
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; WAVE32: [[COPY3:%[0-9]+]]:sreg_32_xm0_xexec = COPY $scc
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; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[COPY3]], implicit $exec
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; WAVE32: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%0:vgpr(p1) = COPY $vgpr0_vgpr1
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%1:vgpr(s32) = COPY $vgpr2
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%2:vgpr(s32) = COPY $vgpr3
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%3:vcc(s1) = COPY $scc
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%5:vgpr(s32) = G_SELECT %3, %1, %2
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G_STORE %5, %0 :: (store 4, addrspace 1)
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...
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