forked from OSchip/llvm-project
[ConstantFolding] add tests for integer min/max intrinsics; NFC
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@ -1,5 +1,5 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instcombine -S -o - %s | FileCheck %s
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; RUN: opt -constprop -S < %s | FileCheck %s
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declare float @llvm.minnum.f32(float, float)
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declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>)
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@ -13,6 +13,18 @@ declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>)
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declare float @llvm.maximum.f32(float, float)
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declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>)
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declare i8 @llvm.smax.i8(i8, i8)
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declare <5 x i8> @llvm.smax.v5i8(<5 x i8>, <5 x i8>)
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declare i8 @llvm.smin.i8(i8, i8)
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declare <5 x i8> @llvm.smin.v5i8(<5 x i8>, <5 x i8>)
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declare i8 @llvm.umax.i8(i8, i8)
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declare <5 x i8> @llvm.umax.v5i8(<5 x i8>, <5 x i8>)
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declare i8 @llvm.umin.i8(i8, i8)
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declare <5 x i8> @llvm.umin.v5i8(<5 x i8>, <5 x i8>)
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define float @minnum_float() {
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; CHECK-LABEL: @minnum_float(
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; CHECK-NEXT: ret float 5.000000e+00
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@ -124,3 +136,75 @@ define <4 x float> @maximum_float_zeros_vec() {
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%1 = call <4 x float> @llvm.maximum.v4f32(<4 x float> <float 0.0, float -0.0, float 0.0, float -0.0>, <4 x float> <float 0.0, float 0.0, float -0.0, float -0.0>)
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ret <4 x float> %1
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}
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define i8 @smax() {
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; CHECK-LABEL: @smax(
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; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.smax.i8(i8 -128, i8 -127)
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; CHECK-NEXT: ret i8 [[R]]
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;
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%r = call i8 @llvm.smax.i8(i8 128, i8 129)
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ret i8 %r
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}
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define <5 x i8> @smax_vec() {
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; CHECK-LABEL: @smax_vec(
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; CHECK-NEXT: [[R:%.*]] = call <5 x i8> @llvm.smax.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 127>)
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; CHECK-NEXT: ret <5 x i8> [[R]]
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;
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%r = call <5 x i8> @llvm.smax.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 127>)
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ret <5 x i8> %r
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}
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define i8 @smin() {
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; CHECK-LABEL: @smin(
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; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.smin.i8(i8 -128, i8 127)
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; CHECK-NEXT: ret i8 [[R]]
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;
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%r = call i8 @llvm.smin.i8(i8 128, i8 127)
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ret i8 %r
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}
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define <5 x i8> @smin_vec() {
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; CHECK-LABEL: @smin_vec(
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; CHECK-NEXT: [[R:%.*]] = call <5 x i8> @llvm.smin.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 -127>)
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; CHECK-NEXT: ret <5 x i8> [[R]]
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;
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%r = call <5 x i8> @llvm.smin.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 129>)
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ret <5 x i8> %r
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}
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define i8 @umax() {
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; CHECK-LABEL: @umax(
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; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.umax.i8(i8 -128, i8 127)
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; CHECK-NEXT: ret i8 [[R]]
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;
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%r = call i8 @llvm.umax.i8(i8 128, i8 127)
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ret i8 %r
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}
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define <5 x i8> @umax_vec() {
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; CHECK-LABEL: @umax_vec(
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; CHECK-NEXT: [[R:%.*]] = call <5 x i8> @llvm.umax.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 -128>)
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; CHECK-NEXT: ret <5 x i8> [[R]]
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;
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%r = call <5 x i8> @llvm.umax.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 128>)
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ret <5 x i8> %r
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}
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define i8 @umin() {
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; CHECK-LABEL: @umin(
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; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.umin.i8(i8 -128, i8 127)
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; CHECK-NEXT: ret i8 [[R]]
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;
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%r = call i8 @llvm.umin.i8(i8 128, i8 127)
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ret i8 %r
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}
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define <5 x i8> @umin_vec() {
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; CHECK-LABEL: @umin_vec(
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; CHECK-NEXT: [[R:%.*]] = call <5 x i8> @llvm.umin.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 -128>)
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; CHECK-NEXT: ret <5 x i8> [[R]]
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;
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%r = call <5 x i8> @llvm.umin.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 128>)
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ret <5 x i8> %r
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}
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