From 9f958958334f380c675b832e8207304dfe0a874f Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Wed, 29 Jul 2020 09:44:51 -0400
Subject: [PATCH] [ConstantFolding] add tests for integer min/max intrinsics;
 NFC

---
 llvm/test/Analysis/ConstantFolding/min-max.ll | 86 ++++++++++++++++++-
 1 file changed, 85 insertions(+), 1 deletion(-)

diff --git a/llvm/test/Analysis/ConstantFolding/min-max.ll b/llvm/test/Analysis/ConstantFolding/min-max.ll
index 5ba95c3aeb5c..26952926ccc9 100644
--- a/llvm/test/Analysis/ConstantFolding/min-max.ll
+++ b/llvm/test/Analysis/ConstantFolding/min-max.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -instcombine -S -o - %s | FileCheck %s
+; RUN: opt -constprop -S < %s | FileCheck %s
 
 declare float @llvm.minnum.f32(float, float)
 declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>)
@@ -13,6 +13,18 @@ declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>)
 declare float @llvm.maximum.f32(float, float)
 declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>)
 
+declare i8 @llvm.smax.i8(i8, i8)
+declare <5 x i8> @llvm.smax.v5i8(<5 x i8>, <5 x i8>)
+
+declare i8 @llvm.smin.i8(i8, i8)
+declare <5 x i8> @llvm.smin.v5i8(<5 x i8>, <5 x i8>)
+
+declare i8 @llvm.umax.i8(i8, i8)
+declare <5 x i8> @llvm.umax.v5i8(<5 x i8>, <5 x i8>)
+
+declare i8 @llvm.umin.i8(i8, i8)
+declare <5 x i8> @llvm.umin.v5i8(<5 x i8>, <5 x i8>)
+
 define float @minnum_float() {
 ; CHECK-LABEL: @minnum_float(
 ; CHECK-NEXT:    ret float 5.000000e+00
@@ -124,3 +136,75 @@ define <4 x float> @maximum_float_zeros_vec() {
   %1 = call <4 x float> @llvm.maximum.v4f32(<4 x float> <float 0.0, float -0.0, float 0.0, float -0.0>, <4 x float> <float 0.0, float 0.0, float -0.0, float -0.0>)
   ret <4 x float> %1
 }
+
+define i8 @smax() {
+; CHECK-LABEL: @smax(
+; CHECK-NEXT:    [[R:%.*]] = call i8 @llvm.smax.i8(i8 -128, i8 -127)
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %r = call i8 @llvm.smax.i8(i8 128, i8 129)
+  ret i8 %r
+}
+
+define <5 x i8> @smax_vec() {
+; CHECK-LABEL: @smax_vec(
+; CHECK-NEXT:    [[R:%.*]] = call <5 x i8> @llvm.smax.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 127>)
+; CHECK-NEXT:    ret <5 x i8> [[R]]
+;
+  %r = call <5 x i8> @llvm.smax.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 127>)
+  ret <5 x i8> %r
+}
+
+define i8 @smin() {
+; CHECK-LABEL: @smin(
+; CHECK-NEXT:    [[R:%.*]] = call i8 @llvm.smin.i8(i8 -128, i8 127)
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %r = call i8 @llvm.smin.i8(i8 128, i8 127)
+  ret i8 %r
+}
+
+define <5 x i8> @smin_vec() {
+; CHECK-LABEL: @smin_vec(
+; CHECK-NEXT:    [[R:%.*]] = call <5 x i8> @llvm.smin.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 -127>)
+; CHECK-NEXT:    ret <5 x i8> [[R]]
+;
+  %r = call <5 x i8> @llvm.smin.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 129>)
+  ret <5 x i8> %r
+}
+
+define i8 @umax() {
+; CHECK-LABEL: @umax(
+; CHECK-NEXT:    [[R:%.*]] = call i8 @llvm.umax.i8(i8 -128, i8 127)
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %r = call i8 @llvm.umax.i8(i8 128, i8 127)
+  ret i8 %r
+}
+
+define <5 x i8> @umax_vec() {
+; CHECK-LABEL: @umax_vec(
+; CHECK-NEXT:    [[R:%.*]] = call <5 x i8> @llvm.umax.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 -128>)
+; CHECK-NEXT:    ret <5 x i8> [[R]]
+;
+  %r = call <5 x i8> @llvm.umax.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 128>)
+  ret <5 x i8> %r
+}
+
+define i8 @umin() {
+; CHECK-LABEL: @umin(
+; CHECK-NEXT:    [[R:%.*]] = call i8 @llvm.umin.i8(i8 -128, i8 127)
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %r = call i8 @llvm.umin.i8(i8 128, i8 127)
+  ret i8 %r
+}
+
+define <5 x i8> @umin_vec() {
+; CHECK-LABEL: @umin_vec(
+; CHECK-NEXT:    [[R:%.*]] = call <5 x i8> @llvm.umin.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 -128>)
+; CHECK-NEXT:    ret <5 x i8> [[R]]
+;
+  %r = call <5 x i8> @llvm.umin.v5i8(<5 x i8> <i8 undef, i8 undef, i8 1, i8 42, i8 42>, <5 x i8> <i8 undef, i8 1, i8 undef, i8 42, i8 128>)
+  ret <5 x i8> %r
+}