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[X86][SSE] Update MOVNTDQA non-temporal loads to generic implementation (clang) 

MOVNTDQA non-temporal aligned vector loads can be correctly represented using generic builtin loads, allowing us to remove the existing x86 intrinsics.

LLVM companion patch: D31767.

Differential Revision: https://reviews.llvm.org/D31766

llvm-svn: 300326
This commit is contained in:
Simon Pilgrim 2017-04-14 15:05:57 +00:00
parent 5a22eaa2bf
commit 9f6e79c5e4
7 changed files with 6 additions and 9 deletions
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3
clang/include/clang/Basic/BuiltinsX86.def
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@ -391,7 +391,6 @@ TARGET_BUILTIN(__builtin_ia32_roundsd, "V2dV2dV2dIi", "", "sse4.1")
TARGET_BUILTIN(__builtin_ia32_roundpd, "V2dV2dIi", "", "sse4.1")
TARGET_BUILTIN(__builtin_ia32_dpps, "V4fV4fV4fIc", "", "sse4.1")
TARGET_BUILTIN(__builtin_ia32_dppd, "V2dV2dV2dIc", "", "sse4.1")
TARGET_BUILTIN(__builtin_ia32_movntdqa, "V2LLiV2LLiC*", "", "sse4.1")
TARGET_BUILTIN(__builtin_ia32_ptestz128, "iV2LLiV2LLi", "", "sse4.1")
TARGET_BUILTIN(__builtin_ia32_ptestc128, "iV2LLiV2LLi", "", "sse4.1")
TARGET_BUILTIN(__builtin_ia32_ptestnzc128, "iV2LLiV2LLi", "", "sse4.1")
@ -576,7 +575,6 @@ TARGET_BUILTIN(__builtin_ia32_psrldi256, "V8iV8ii", "", "avx2")
TARGET_BUILTIN(__builtin_ia32_psrld256, "V8iV8iV4i", "", "avx2")
TARGET_BUILTIN(__builtin_ia32_psrlqi256, "V4LLiV4LLii", "", "avx2")
TARGET_BUILTIN(__builtin_ia32_psrlq256, "V4LLiV4LLiV2LLi", "", "avx2")
TARGET_BUILTIN(__builtin_ia32_movntdqa256, "V4LLiV4LLiC*", "", "avx2")
TARGET_BUILTIN(__builtin_ia32_permvarsi256, "V8iV8iV8i", "", "avx2")
TARGET_BUILTIN(__builtin_ia32_permvarsf256, "V8fV8fV8i", "", "avx2")
TARGET_BUILTIN(__builtin_ia32_permti256, "V4LLiV4LLiV4LLiIc", "", "avx2")
@ -1747,7 +1745,6 @@ TARGET_BUILTIN(__builtin_ia32_kortestzhi, "iUsUs","","avx512f")
TARGET_BUILTIN(__builtin_ia32_kunpckhi, "UsUsUs","","avx512f")
TARGET_BUILTIN(__builtin_ia32_kxnorhi, "UsUsUs","","avx512f")
TARGET_BUILTIN(__builtin_ia32_kxorhi, "UsUsUs","","avx512f")
TARGET_BUILTIN(__builtin_ia32_movntdqa512, "V8LLiV8LLi*","","avx512f")
TARGET_BUILTIN(__builtin_ia32_palignr512_mask, "V64cV64cV64cIiV64cULLi","","avx512bw")
TARGET_BUILTIN(__builtin_ia32_dbpsadbw128_mask, "V8sV16cV16cIiV8sUc","","avx512bw,avx512vl")
TARGET_BUILTIN(__builtin_ia32_dbpsadbw256_mask, "V16sV32cV32cIiV16sUs","","avx512bw,avx512vl")

2
clang/lib/Headers/avx2intrin.h
View File

@ -832,7 +832,7 @@ _mm256_xor_si256(__m256i __a, __m256i __b)
static __inline__ __m256i __DEFAULT_FN_ATTRS
_mm256_stream_load_si256(__m256i const *__V)
{
return (__m256i)__builtin_ia32_movntdqa256((const __v4di *)__V);
return (__m256i)__builtin_nontemporal_load((const __v4di *)__V);
}
static __inline__ __m128 __DEFAULT_FN_ATTRS

2
clang/lib/Headers/avx512fintrin.h
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@ -8931,7 +8931,7 @@ _mm512_stream_si512 (__m512i * __P, __m512i __A)
static __inline__ __m512i __DEFAULT_FN_ATTRS
_mm512_stream_load_si512 (void *__P)
{
return __builtin_ia32_movntdqa512 ((__v8di *)__P);
return (__m512i) __builtin_nontemporal_load((const __v8di *)__P);
}
static __inline__ void __DEFAULT_FN_ATTRS

2
clang/lib/Headers/smmintrin.h
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@ -691,7 +691,7 @@ _mm_mul_epi32 (__m128i __V1, __m128i __V2)
static __inline__ __m128i __DEFAULT_FN_ATTRS
_mm_stream_load_si128 (__m128i const *__V)
{
return (__m128i) __builtin_ia32_movntdqa ((const __v2di *) __V);
return (__m128i) __builtin_nontemporal_load ((const __v2di *) __V);
}
/* SSE4 Packed Integer Min/Max Instructions. */

2
clang/test/CodeGen/avx2-builtins.c
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@ -1117,7 +1117,7 @@ __m256i test_mm256_srlv_epi64(__m256i a, __m256i b) {
__m256i test_mm256_stream_load_si256(__m256i const *a) {
// CHECK-LABEL: test_mm256_stream_load_si256
// CHECK: call <4 x i64> @llvm.x86.avx2.movntdqa(i8* %{{.*}})
// CHECK: load <4 x i64>, <4 x i64>* %{{.*}}, align 32, !nontemporal
return _mm256_stream_load_si256(a);
}

2
clang/test/CodeGen/avx512f-builtins.c
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@ -6251,7 +6251,7 @@ void test_mm512_stream_si512(__m512i * __P, __m512i __A) {
__m512i test_mm512_stream_load_si512(void *__P) {
// CHECK-LABEL: @test_mm512_stream_load_si512
// CHECK: @llvm.x86.avx512.movntdqa
// CHECK: load <8 x i64>, <8 x i64>* %{{.*}}, align 64, !nontemporal
return _mm512_stream_load_si512(__P);
}

2
clang/test/CodeGen/sse41-builtins.c
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@ -354,7 +354,7 @@ __m128 test_mm_round_ss(__m128 x, __m128 y) {
__m128i test_mm_stream_load_si128(__m128i const *a) {
// CHECK-LABEL: test_mm_stream_load_si128
// CHECK: call <2 x i64> @llvm.x86.sse41.movntdqa(i8* %{{.*}})
// CHECK: load <2 x i64>, <2 x i64>* %{{.*}}, align 16, !nontemporal
return _mm_stream_load_si128(a);
}