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AMDGPU/SILoadStoreOptimizer: Add const to more functions 

Reviewers: arsenm, pendingchaos, rampitec, nhaehnle, vpykhtin

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65901

llvm-svn: 372298
This commit is contained in:
Tom Stellard 2019-09-19 04:39:45 +00:00
parent bffbeecb44
commit 9f4c7571a1
1 changed files with 12 additions and 12 deletions
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24
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
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@ -183,17 +183,17 @@ private:
MachineBasicBlock::iterator mergeBufferStorePair(CombineInfo &CI); MachineBasicBlock::iterator mergeBufferStorePair(CombineInfo &CI);
void updateBaseAndOffset(MachineInstr &I, unsigned NewBase, void updateBaseAndOffset(MachineInstr &I, unsigned NewBase,
int32_t NewOffset); int32_t NewOffset) const;
unsigned computeBase(MachineInstr &MI, const MemAddress &Addr); unsigned computeBase(MachineInstr &MI, const MemAddress &Addr) const;
MachineOperand createRegOrImm(int32_t Val, MachineInstr &MI); MachineOperand createRegOrImm(int32_t Val, MachineInstr &MI) const;
Optional<int32_t> extractConstOffset(const MachineOperand &Op); Optional<int32_t> extractConstOffset(const MachineOperand &Op) const;
void processBaseWithConstOffset(const MachineOperand &Base, MemAddress &Addr); void processBaseWithConstOffset(const MachineOperand &Base, MemAddress &Addr) const;
/// Promotes constant offset to the immediate by adjusting the base. It /// Promotes constant offset to the immediate by adjusting the base. It
/// tries to use a base from the nearby instructions that allows it to have /// tries to use a base from the nearby instructions that allows it to have
/// a 13bit constant offset which gets promoted to the immediate. /// a 13bit constant offset which gets promoted to the immediate.
bool promoteConstantOffsetToImm(MachineInstr &CI, bool promoteConstantOffsetToImm(MachineInstr &CI,
MemInfoMap &Visited, MemInfoMap &Visited,
SmallPtrSet<MachineInstr *, 4> &Promoted); SmallPtrSet<MachineInstr *, 4> &Promoted) const;
public: public:
static char ID; static char ID;
@ -1151,7 +1151,7 @@ SILoadStoreOptimizer::mergeBufferStorePair(CombineInfo &CI) {
} }
MachineOperand MachineOperand
SILoadStoreOptimizer::createRegOrImm(int32_t Val, MachineInstr &MI) { SILoadStoreOptimizer::createRegOrImm(int32_t Val, MachineInstr &MI) const {
APInt V(32, Val, true); APInt V(32, Val, true);
if (TII->isInlineConstant(V)) if (TII->isInlineConstant(V))
return MachineOperand::CreateImm(Val); return MachineOperand::CreateImm(Val);
@ -1168,7 +1168,7 @@ SILoadStoreOptimizer::createRegOrImm(int32_t Val, MachineInstr &MI) {
// Compute base address using Addr and return the final register. // Compute base address using Addr and return the final register.
unsigned SILoadStoreOptimizer::computeBase(MachineInstr &MI, unsigned SILoadStoreOptimizer::computeBase(MachineInstr &MI,
const MemAddress &Addr) { const MemAddress &Addr) const {
MachineBasicBlock *MBB = MI.getParent(); MachineBasicBlock *MBB = MI.getParent();
MachineBasicBlock::iterator MBBI = MI.getIterator(); MachineBasicBlock::iterator MBBI = MI.getIterator();
DebugLoc DL = MI.getDebugLoc(); DebugLoc DL = MI.getDebugLoc();
@ -1227,13 +1227,13 @@ unsigned SILoadStoreOptimizer::computeBase(MachineInstr &MI,
// Update base and offset with the NewBase and NewOffset in MI. // Update base and offset with the NewBase and NewOffset in MI.
void SILoadStoreOptimizer::updateBaseAndOffset(MachineInstr &MI, void SILoadStoreOptimizer::updateBaseAndOffset(MachineInstr &MI,
unsigned NewBase, unsigned NewBase,
int32_t NewOffset) { int32_t NewOffset) const {
TII->getNamedOperand(MI, AMDGPU::OpName::vaddr)->setReg(NewBase); TII->getNamedOperand(MI, AMDGPU::OpName::vaddr)->setReg(NewBase);
TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset); TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset);
} }
Optional<int32_t> Optional<int32_t>
SILoadStoreOptimizer::extractConstOffset(const MachineOperand &Op) { SILoadStoreOptimizer::extractConstOffset(const MachineOperand &Op) const {
if (Op.isImm()) if (Op.isImm())
return Op.getImm(); return Op.getImm();
@ -1259,7 +1259,7 @@ SILoadStoreOptimizer::extractConstOffset(const MachineOperand &Op) {
// %Base:vreg_64 = // %Base:vreg_64 =
// REG_SEQUENCE %LO:vgpr_32, %subreg.sub0, %HI:vgpr_32, %subreg.sub1 // REG_SEQUENCE %LO:vgpr_32, %subreg.sub0, %HI:vgpr_32, %subreg.sub1
void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base, void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base,
MemAddress &Addr) { MemAddress &Addr) const {
if (!Base.isReg()) if (!Base.isReg())
return; return;
@ -1314,7 +1314,7 @@ void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base
bool SILoadStoreOptimizer::promoteConstantOffsetToImm( bool SILoadStoreOptimizer::promoteConstantOffsetToImm(
MachineInstr &MI, MachineInstr &MI,
MemInfoMap &Visited, MemInfoMap &Visited,
SmallPtrSet<MachineInstr *, 4> &AnchorList) { SmallPtrSet<MachineInstr *, 4> &AnchorList) const {
if (!(MI.mayLoad() ^ MI.mayStore())) if (!(MI.mayLoad() ^ MI.mayStore()))
return false; return false;