forked from OSchip/llvm-project
[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.
llvm-svn: 205876
This commit is contained in:
Bradley Smith
parent
e8b4166acc
commit
9f29b726d5
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@ -2516,6 +2516,12 @@ bool ARM64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
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} else if (!Op.compare_lower("ipas2le1")) {
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// SYS #4, C8, C4, #5
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SYS_ALIAS(4, 8, 4, 5);
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} else if (!Op.compare_lower("ipas2e1is")) {
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// SYS #4, C8, C4, #1
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SYS_ALIAS(4, 8, 0, 1);
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} else if (!Op.compare_lower("ipas2le1is")) {
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// SYS #4, C8, C4, #5
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SYS_ALIAS(4, 8, 0, 5);
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} else if (!Op.compare_lower("vmalls12e1")) {
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// SYS #4, C8, C7, #6
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SYS_ALIAS(4, 8, 7, 6);
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@ -2531,12 +2537,17 @@ bool ARM64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
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Parser.Lex(); // Eat operand.
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bool ExpectRegister = (Op.lower().find("all") == StringRef::npos);
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bool HasRegister = false;
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// Check for the optional register operand.
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if (getLexer().is(AsmToken::Comma)) {
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Parser.Lex(); // Eat comma.
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if (Tok.isNot(AsmToken::Identifier) || parseRegister(Operands))
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return TokError("expected register operand");
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HasRegister = true;
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}
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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@ -2544,6 +2555,13 @@ bool ARM64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
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return TokError("unexpected token in argument list");
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}
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if (ExpectRegister && !HasRegister) {
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return TokError("specified " + Mnemonic + " op requires a register");
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}
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else if (!ExpectRegister && HasRegister) {
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return TokError("specified " + Mnemonic + " op does not use a register");
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}
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Parser.Lex(); // Consume the EndOfStatement
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return false;
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}
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@ -849,6 +849,20 @@ bool ARM64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
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break;
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}
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break;
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case 0:
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switch (Op1Val) {
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default:
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break;
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case 4:
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switch (Op2Val) {
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default:
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break;
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case 1: Asm = "tlbi\tipas2e1is"; break;
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case 5: Asm = "tlbi\tipas2le1is"; break;
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}
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break;
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}
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break;
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case 4:
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switch (Op1Val) {
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default:
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@ -412,120 +412,128 @@ foo:
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; CHECK: tlbi ipas2e1
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sys #4, c8, c4, #5
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; CHECK: tlbi ipas2le1
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sys #4, c8, c0, #1
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; CHECK: tlbi ipas2e1is
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sys #4, c8, c0, #5
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; CHECK: tlbi ipas2le1is
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sys #4, c8, c7, #6
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; CHECK: tlbi vmalls12e1
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sys #4, c8, c3, #6
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; CHECK: tlbi vmalls12e1is
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ic ialluis
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; CHECK: ic ialluis
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; CHECK: ic ialluis ; encoding: [0x1f,0x71,0x08,0xd5]
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ic iallu
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; CHECK: ic iallu
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ic ivau
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; CHECK: ic ivau
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; CHECK: ic iallu ; encoding: [0x1f,0x75,0x08,0xd5]
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ic ivau, x0
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; CHECK: ic ivau, x0 ; encoding: [0x20,0x75,0x0b,0xd5]
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dc zva
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; CHECK: dc zva
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dc ivac
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; CHECK: dc ivac
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dc isw
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; CHECK: dc isw
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dc cvac
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; CHECK: dc cvac
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dc csw
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; CHECK: dc csw
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dc cvau
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; CHECK: dc cvau
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dc civac
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; CHECK: dc civac
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dc cisw
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; CHECK: dc cisw
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dc zva, x0
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; CHECK: dc zva, x0 ; encoding: [0x20,0x74,0x0b,0xd5]
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dc ivac, x0
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; CHECK: dc ivac, x0 ; encoding: [0x20,0x76,0x08,0xd5]
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dc isw, x0
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; CHECK: dc isw, x0 ; encoding: [0x40,0x76,0x08,0xd5]
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dc cvac, x0
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; CHECK: dc cvac, x0 ; encoding: [0x20,0x7a,0x0b,0xd5]
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dc csw, x0
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; CHECK: dc csw, x0 ; encoding: [0x40,0x7a,0x08,0xd5]
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dc cvau, x0
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; CHECK: dc cvau, x0 ; encoding: [0x20,0x7b,0x0b,0xd5]
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dc civac, x0
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; CHECK: dc civac, x0 ; encoding: [0x20,0x7e,0x0b,0xd5]
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dc cisw, x0
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; CHECK: dc cisw, x0 ; encoding: [0x40,0x7e,0x08,0xd5]
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at s1e1r
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; CHECK: at s1e1r
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at s1e2r
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; CHECK: at s1e2r
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at s1e3r
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; CHECK: at s1e3r
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at s1e1w
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; CHECK: at s1e1w
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at s1e2w
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; CHECK: at s1e2w
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at s1e3w
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; CHECK: at s1e3w
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at s1e0r
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; CHECK: at s1e0r
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at s1e0w
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; CHECK: at s1e0w
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at s12e1r
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; CHECK: at s12e1r
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at s12e1w
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; CHECK: at s12e1w
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at s12e0r
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; CHECK: at s12e0r
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at s12e0w
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; CHECK: at s12e0w
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at s1e1r, x0
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; CHECK: at s1e1r, x0 ; encoding: [0x00,0x78,0x08,0xd5]
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at s1e2r, x0
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; CHECK: at s1e2r, x0 ; encoding: [0x00,0x78,0x0c,0xd5]
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at s1e3r, x0
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; CHECK: at s1e3r, x0 ; encoding: [0x00,0x78,0x0e,0xd5]
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at s1e1w, x0
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; CHECK: at s1e1w, x0 ; encoding: [0x20,0x78,0x08,0xd5]
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at s1e2w, x0
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; CHECK: at s1e2w, x0 ; encoding: [0x20,0x78,0x0c,0xd5]
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at s1e3w, x0
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; CHECK: at s1e3w, x0 ; encoding: [0x20,0x78,0x0e,0xd5]
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at s1e0r, x0
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; CHECK: at s1e0r, x0 ; encoding: [0x40,0x78,0x08,0xd5]
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at s1e0w, x0
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; CHECK: at s1e0w, x0 ; encoding: [0x60,0x78,0x08,0xd5]
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at s12e1r, x0
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; CHECK: at s12e1r, x0 ; encoding: [0x80,0x78,0x0c,0xd5]
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at s12e1w, x0
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; CHECK: at s12e1w, x0 ; encoding: [0xa0,0x78,0x0c,0xd5]
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at s12e0r, x0
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; CHECK: at s12e0r, x0 ; encoding: [0xc0,0x78,0x0c,0xd5]
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at s12e0w, x0
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; CHECK: at s12e0w, x0 ; encoding: [0xe0,0x78,0x0c,0xd5]
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tlbi vmalle1is
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; CHECK: tlbi vmalle1is
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; CHECK: tlbi vmalle1is ; encoding: [0x1f,0x83,0x08,0xd5]
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tlbi alle2is
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; CHECK: tlbi alle2is
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; CHECK: tlbi alle2is ; encoding: [0x1f,0x83,0x0c,0xd5]
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tlbi alle3is
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; CHECK: tlbi alle3is
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tlbi vae1is
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; CHECK: tlbi vae1is
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tlbi vae2is
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; CHECK: tlbi vae2is
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tlbi vae3is
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; CHECK: tlbi vae3is
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tlbi aside1is
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; CHECK: tlbi aside1is
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tlbi vaae1is
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; CHECK: tlbi vaae1is
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; CHECK: tlbi alle3is ; encoding: [0x1f,0x83,0x0e,0xd5]
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tlbi vae1is, x0
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; CHECK: tlbi vae1is, x0 ; encoding: [0x20,0x83,0x08,0xd5]
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tlbi vae2is, x0
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; CHECK: tlbi vae2is, x0 ; encoding: [0x20,0x83,0x0c,0xd5]
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tlbi vae3is, x0
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; CHECK: tlbi vae3is, x0 ; encoding: [0x20,0x83,0x0e,0xd5]
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tlbi aside1is, x0
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; CHECK: tlbi aside1is, x0 ; encoding: [0x40,0x83,0x08,0xd5]
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tlbi vaae1is, x0
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; CHECK: tlbi vaae1is, x0 ; encoding: [0x60,0x83,0x08,0xd5]
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tlbi alle1is
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; CHECK: tlbi alle1is
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tlbi vale1is
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; CHECK: tlbi vale1is
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tlbi vaale1is
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; CHECK: tlbi vaale1is
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; CHECK: tlbi alle1is ; encoding: [0x9f,0x83,0x0c,0xd5]
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tlbi vale1is, x0
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; CHECK: tlbi vale1is, x0 ; encoding: [0xa0,0x83,0x08,0xd5]
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tlbi vaale1is, x0
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; CHECK: tlbi vaale1is, x0 ; encoding: [0xe0,0x83,0x08,0xd5]
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tlbi vmalle1
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; CHECK: tlbi vmalle1
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; CHECK: tlbi vmalle1 ; encoding: [0x1f,0x87,0x08,0xd5]
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tlbi alle2
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; CHECK: tlbi alle2
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tlbi vale2is
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; CHECK: tlbi vale2is
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tlbi vale3is
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; CHECK: tlbi vale3is
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; CHECK: tlbi alle2 ; encoding: [0x1f,0x87,0x0c,0xd5]
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tlbi vale2is, x0
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; CHECK: tlbi vale2is, x0 ; encoding: [0xa0,0x83,0x0c,0xd5]
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tlbi vale3is, x0
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; CHECK: tlbi vale3is, x0 ; encoding: [0xa0,0x83,0x0e,0xd5]
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tlbi alle3
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; CHECK: tlbi alle3
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tlbi vae1
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; CHECK: tlbi vae1
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tlbi vae2
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; CHECK: tlbi vae2
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tlbi vae3
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; CHECK: tlbi vae3
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tlbi aside1
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; CHECK: tlbi aside1
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tlbi vaae1
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; CHECK: tlbi vaae1
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; CHECK: tlbi alle3 ; encoding: [0x1f,0x87,0x0e,0xd5]
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tlbi vae1, x0
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; CHECK: tlbi vae1, x0 ; encoding: [0x20,0x87,0x08,0xd5]
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tlbi vae2, x0
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; CHECK: tlbi vae2, x0 ; encoding: [0x20,0x87,0x0c,0xd5]
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tlbi vae3, x0
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; CHECK: tlbi vae3, x0 ; encoding: [0x20,0x87,0x0e,0xd5]
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tlbi aside1, x0
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; CHECK: tlbi aside1, x0 ; encoding: [0x40,0x87,0x08,0xd5]
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tlbi vaae1, x0
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; CHECK: tlbi vaae1, x0 ; encoding: [0x60,0x87,0x08,0xd5]
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tlbi alle1
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; CHECK: tlbi alle1
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tlbi vale1
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; CHECK: tlbi vale1
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tlbi vale2
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; CHECK: tlbi vale2
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tlbi vale3
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; CHECK: tlbi vale3
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tlbi vaale1
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; CHECK: tlbi vaale1
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tlbi ipas2e1, x10
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; CHECK: tlbi ipas2e1, x10
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tlbi ipas2le1, x1
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; CHECK: tlbi ipas2le1, x1
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; CHECK: tlbi alle1 ; encoding: [0x9f,0x87,0x0c,0xd5
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tlbi vale1, x0
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; CHECK: tlbi vale1, x0 ; encoding: [0xa0,0x87,0x08,0xd5]
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tlbi vale2, x0
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; CHECK: tlbi vale2, x0 ; encoding: [0xa0,0x87,0x0c,0xd5]
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tlbi vale3, x0
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; CHECK: tlbi vale3, x0 ; encoding: [0xa0,0x87,0x0e,0xd5]
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tlbi vaale1, x0
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; CHECK: tlbi vaale1, x0 ; encoding: [0xe0,0x87,0x08,0xd5]
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tlbi ipas2e1, x0
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; CHECK: tlbi ipas2e1, x0 ; encoding: [0x20,0x84,0x0c,0xd5]
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tlbi ipas2le1, x0
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; CHECK: tlbi ipas2le1, x0 ; encoding: [0xa0,0x84,0x0c,0xd5]
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tlbi ipas2e1is, x0
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; CHECK: tlbi ipas2e1is, x0 ; encoding: [0x20,0x80,0x0c,0xd5]
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tlbi ipas2le1is, x0
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; CHECK: tlbi ipas2le1is, x0 ; encoding: [0xa0,0x80,0x0c,0xd5]
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tlbi vmalls12e1
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; CHECK: tlbi vmalls12e1
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; CHECK: tlbi vmalls12e1 ; encoding: [0xdf,0x87,0x0c,0xd5]
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tlbi vmalls12e1is
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; CHECK: tlbi vmalls12e1is
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; CHECK: tlbi vmalls12e1is ; encoding: [0xdf,0x83,0x0c,0xd5]
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;-----------------------------------------------------------------------------
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; 5.8.5 Vector Arithmetic aliases
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@ -240,3 +240,103 @@ b.c #0x4
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; CHECK-ERRORS: error: invalid condition code
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; CHECK-ERRORS: b.c #0x4
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; CHECK-ERRORS: ^
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ic ialluis, x0
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; CHECK-ERRORS: error: specified ic op does not use a register
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ic iallu, x0
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; CHECK-ERRORS: error: specified ic op does not use a register
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ic ivau
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; CHECK-ERRORS: error: specified ic op requires a register
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dc zva
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; CHECK-ERRORS: error: specified dc op requires a register
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dc ivac
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; CHECK-ERRORS: error: specified dc op requires a register
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dc isw
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; CHECK-ERRORS: error: specified dc op requires a register
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dc cvac
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; CHECK-ERRORS: error: specified dc op requires a register
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dc csw
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; CHECK-ERRORS: error: specified dc op requires a register
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dc cvau
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; CHECK-ERRORS: error: specified dc op requires a register
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dc civac
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; CHECK-ERRORS: error: specified dc op requires a register
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dc cisw
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; CHECK-ERRORS: error: specified dc op requires a register
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at s1e1r
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e2r
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e3r
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e1w
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e2w
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e3w
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e0r
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; CHECK-ERRORS: error: specified at op requires a register
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at s1e0w
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; CHECK-ERRORS: error: specified at op requires a register
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at s12e1r
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; CHECK-ERRORS: error: specified at op requires a register
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at s12e1w
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; CHECK-ERRORS: error: specified at op requires a register
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at s12e0r
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; CHECK-ERRORS: error: specified at op requires a register
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at s12e0w
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; CHECK-ERRORS: error: specified at op requires a register
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tlbi vmalle1is, x0
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; CHECK-ERRORS: error: specified tlbi op does not use a register
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tlbi vmalle1, x0
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; CHECK-ERRORS: error: specified tlbi op does not use a register
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tlbi alle1is, x0
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; CHECK-ERRORS: error: specified tlbi op does not use a register
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tlbi alle2is, x0
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; CHECK-ERRORS: error: specified tlbi op does not use a register
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tlbi alle3is, x0
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; CHECK-ERRORS: error: specified tlbi op does not use a register
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tlbi alle1, x0
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; CHECK-ERRORS: error: specified tlbi op does not use a register
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tlbi alle2, x0
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; CHECK-ERRORS: error: specified tlbi op does not use a register
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tlbi alle3, x0
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; CHECK-ERRORS: error: specified tlbi op does not use a register
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tlbi vae1is
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; CHECK-ERRORS: error: specified tlbi op requires a register
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tlbi vae2is
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; CHECK-ERRORS: error: specified tlbi op requires a register
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tlbi vae3is
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; CHECK-ERRORS: error: specified tlbi op requires a register
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tlbi aside1is
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; CHECK-ERRORS: error: specified tlbi op requires a register
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tlbi vaae1is
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; CHECK-ERRORS: error: specified tlbi op requires a register
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tlbi vale1is
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; CHECK-ERRORS: error: specified tlbi op requires a register
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tlbi vaale1is
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; CHECK-ERRORS: error: specified tlbi op requires a register
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tlbi vale2is
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; CHECK-ERRORS: error: specified tlbi op requires a register
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tlbi vale3is
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; CHECK-ERRORS: error: specified tlbi op requires a register
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tlbi vae1
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; CHECK-ERRORS: error: specified tlbi op requires a register
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tlbi vae2
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; CHECK-ERRORS: error: specified tlbi op requires a register
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tlbi vae3
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; CHECK-ERRORS: error: specified tlbi op requires a register
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tlbi aside1
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; CHECK-ERRORS: error: specified tlbi op requires a register
|
||||
tlbi vaae1
|
||||
; CHECK-ERRORS: error: specified tlbi op requires a register
|
||||
tlbi vale1
|
||||
; CHECK-ERRORS: error: specified tlbi op requires a register
|
||||
tlbi vale2
|
||||
; CHECK-ERRORS: error: specified tlbi op requires a register
|
||||
tlbi vale3
|
||||
; CHECK-ERRORS: error: specified tlbi op requires a register
|
||||
|
|
|
|||
Loading…
Reference in New Issue