forked from OSchip/llvm-project
Fix some indentation (first hunks).
Remove code (last hunk) that miscompiled immediate and's, such as and uint %tmp.30, 4294958079 into andi. r8, r8, 56319 andis. r8, r8, 65535 instead of: li r9, -9217 and r8, r8, r9 The first always generates zero. This fixes espresso. llvm-svn: 23155
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@ -257,34 +257,33 @@ SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
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// Generate Mask value for Target
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if (isIntImmediate(Op0.getOperand(1), Value)) {
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switch(Op0Opc) {
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case ISD::SHL: TgtMask <<= Value; break;
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case ISD::SRL: TgtMask >>= Value; break;
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case ISD::AND: TgtMask &= Value; break;
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case ISD::SHL: TgtMask <<= Value; break;
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case ISD::SRL: TgtMask >>= Value; break;
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case ISD::AND: TgtMask &= Value; break;
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}
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} else {
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return 0;
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}
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// Generate Mask value for Insert
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if (isIntImmediate(Op1.getOperand(1), Value)) {
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switch(Op1Opc) {
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case ISD::SHL:
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SH = Value;
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InsMask <<= SH;
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if (Op0Opc == ISD::SRL) IsRotate = true;
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break;
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case ISD::SRL:
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SH = Value;
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InsMask >>= SH;
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SH = 32-SH;
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if (Op0Opc == ISD::SHL) IsRotate = true;
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break;
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case ISD::AND:
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InsMask &= Value;
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break;
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}
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} else {
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if (!isIntImmediate(Op1.getOperand(1), Value))
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return 0;
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switch(Op1Opc) {
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case ISD::SHL:
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SH = Value;
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InsMask <<= SH;
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if (Op0Opc == ISD::SRL) IsRotate = true;
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break;
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case ISD::SRL:
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SH = Value;
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InsMask >>= SH;
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SH = 32-SH;
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if (Op0Opc == ISD::SHL) IsRotate = true;
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break;
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case ISD::AND:
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InsMask &= Value;
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break;
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}
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// If both of the inputs are ANDs and one of them has a logical shift by
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@ -979,15 +978,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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getI32Imm(MB), getI32Imm(ME));
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break;
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}
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// If this is an and with an immediate that isn't a mask, then codegen it as
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// high and low 16 bit immediate ands.
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if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
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N->getOperand(1),
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PPC::ANDISo, PPC::ANDIo)) {
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CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
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N = I;
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break;
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}
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// Finally, check for the case where we are being asked to select
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// and (not(a), b) or and (a, not(b)) which can be selected as andc.
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if (isOprNot(N->getOperand(0).Val))
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