forked from OSchip/llvm-project
[AMDGPU] Fix FoldImmediate for 16 bit operand
Differential Revision: https://reviews.llvm.org/D79362
This commit is contained in:
Stanislav Mekhanoshin
parent
55b9b11fea
commit
9ef166e657
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@ -2509,15 +2509,41 @@ bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
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unsigned Opc = UseMI.getOpcode();
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if (Opc == AMDGPU::COPY) {
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bool isVGPRCopy = RI.isVGPR(*MRI, UseMI.getOperand(0).getReg());
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Register DstReg = UseMI.getOperand(0).getReg();
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Register SrcReg = UseMI.getOperand(1).getReg();
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bool Is16Bit = getOpSize(UseMI, 0) == 2;
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bool isVGPRCopy = RI.isVGPR(*MRI, DstReg);
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unsigned NewOpc = isVGPRCopy ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
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if (RI.isAGPR(*MRI, UseMI.getOperand(0).getReg())) {
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if (!isInlineConstant(*ImmOp, AMDGPU::OPERAND_REG_INLINE_AC_INT32))
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APInt Imm(32, ImmOp->getImm());
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if (UseMI.getOperand(1).getSubReg() == AMDGPU::hi16)
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Imm = Imm.ashr(16);
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if (RI.isAGPR(*MRI, DstReg)) {
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if (!isInlineConstant(Imm))
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return false;
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NewOpc = AMDGPU::V_ACCVGPR_WRITE_B32;
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}
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if (Is16Bit) {
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if (isVGPRCopy)
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return false; // Do not clobber vgpr_hi16
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if (DstReg.isVirtual() &&
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UseMI.getOperand(0).getSubReg() != AMDGPU::lo16)
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return false;
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UseMI.getOperand(0).setSubReg(0);
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if (DstReg.isPhysical()) {
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DstReg = RI.get32BitRegister(DstReg);
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UseMI.getOperand(0).setReg(DstReg);
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}
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assert(SrcReg.isVirtual());
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}
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UseMI.setDesc(get(NewOpc));
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UseMI.getOperand(1).ChangeToImmediate(ImmOp->getImm());
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UseMI.getOperand(1).ChangeToImmediate(Imm.getSExtValue());
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UseMI.getOperand(1).setTargetFlags(0);
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UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
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return true;
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}
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@ -827,11 +827,7 @@ public:
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const MachineOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg()) {
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if (unsigned SubReg = MO.getSubReg()) {
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assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg(
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MI.getParent()->getParent()->getRegInfo().
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getRegClass(MO.getReg()), SubReg)) >= 32 &&
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"Sub-dword subregs are not supported");
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return RI.getNumChannelsFromSubReg(SubReg) * 4;
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return RI.getSubRegIdxSize(SubReg) / 8;
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}
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}
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return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
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@ -0,0 +1,257 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass peephole-opt -o - %s | FileCheck -check-prefix=GCN %s
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---
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name: fold_simm_16_sub_to_lo
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body: |
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bb.0:
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; GCN-LABEL: name: fold_simm_16_sub_to_lo
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: [[COPY:%[0-9]+]]:sgpr_lo16 = COPY killed [[S_MOV_B32_]].lo16
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; GCN: SI_RETURN_TO_EPILOG [[COPY]]
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%0:sreg_32 = S_MOV_B32 2048
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%1:sgpr_lo16 = COPY killed %0.lo16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_simm_16_sub_to_sub
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body: |
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bb.0:
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; GCN-LABEL: name: fold_simm_16_sub_to_sub
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: SI_RETURN_TO_EPILOG [[S_MOV_B32_1]]
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%0:sreg_32 = S_MOV_B32 2048
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%1.lo16:sreg_32 = COPY killed %0.lo16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_simm_16_sub_to_phys
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body: |
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bb.0:
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; GCN-LABEL: name: fold_simm_16_sub_to_phys
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: $sgpr0 = S_MOV_B32 2048
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; GCN: SI_RETURN_TO_EPILOG $sgpr0_lo16
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%0:sreg_32 = S_MOV_B32 2048
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$sgpr0_lo16 = COPY killed %0.lo16
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SI_RETURN_TO_EPILOG $sgpr0_lo16
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...
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---
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name: fold_aimm_16_sub_to_sub_2048
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body: |
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bb.0:
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; GCN-LABEL: name: fold_aimm_16_sub_to_sub_2048
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: %1.lo16:agpr_32 = COPY killed [[S_MOV_B32_]].lo16
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; GCN: SI_RETURN_TO_EPILOG %1
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%0:sreg_32 = S_MOV_B32 2048
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%1.lo16:agpr_32 = COPY killed %0.lo16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_aimm_16_sub_to_sub_0
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body: |
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bb.0:
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; GCN-LABEL: name: fold_aimm_16_sub_to_sub_0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: [[V_ACCVGPR_WRITE_B32_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32 0, implicit $exec
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; GCN: SI_RETURN_TO_EPILOG [[V_ACCVGPR_WRITE_B32_]]
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%0:sreg_32 = S_MOV_B32 0
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%1.lo16:agpr_32 = COPY killed %0.lo16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_aimm_16_sub_to_phys
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body: |
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bb.0:
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; GCN-LABEL: name: fold_aimm_16_sub_to_phys
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: $agpr0 = V_ACCVGPR_WRITE_B32 0, implicit $exec
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; GCN: SI_RETURN_TO_EPILOG $agpr0_lo16
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%0:sreg_32 = S_MOV_B32 0
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$agpr0_lo16 = COPY killed %0.lo16
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SI_RETURN_TO_EPILOG $agpr0_lo16
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...
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---
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name: fold_vimm_16_sub_to_lo
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body: |
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bb.0:
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; GCN-LABEL: name: fold_vimm_16_sub_to_lo
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: [[COPY:%[0-9]+]]:vgpr_lo16 = COPY killed [[S_MOV_B32_]].lo16
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; GCN: SI_RETURN_TO_EPILOG [[COPY]]
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%0:sreg_32 = S_MOV_B32 2048
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%1:vgpr_lo16 = COPY killed %0.lo16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_vimm_16_sub_to_sub
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body: |
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bb.0:
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; GCN-LABEL: name: fold_vimm_16_sub_to_sub
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: %1.lo16:vgpr_32 = COPY killed [[S_MOV_B32_]].lo16
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; GCN: SI_RETURN_TO_EPILOG %1
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%0:sreg_32 = S_MOV_B32 2048
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%1.lo16:vgpr_32 = COPY killed %0.lo16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_vimm_16_sub_to_phys
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body: |
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bb.0:
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; GCN-LABEL: name: fold_vimm_16_sub_to_phys
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: $vgpr0_lo16 = COPY killed [[S_MOV_B32_]].lo16
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; GCN: SI_RETURN_TO_EPILOG $vgpr0_lo16
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%0:sreg_32 = S_MOV_B32 2048
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$vgpr0_lo16 = COPY killed %0.lo16
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SI_RETURN_TO_EPILOG $vgpr0_lo16
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...
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---
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name: fold_vimm_16_lo_to_hi
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body: |
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bb.0:
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; GCN-LABEL: name: fold_vimm_16_lo_to_hi
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: %1.hi16:vgpr_32 = COPY killed [[S_MOV_B32_]].lo16
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; GCN: SI_RETURN_TO_EPILOG %1
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%0:sreg_32 = S_MOV_B32 2048
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%1.hi16:vgpr_32 = COPY killed %0.lo16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_vimm_16_hi_to_lo
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body: |
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bb.0:
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; GCN-LABEL: name: fold_vimm_16_hi_to_lo
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: %1.lo16:vgpr_32 = COPY killed [[S_MOV_B32_]].hi16
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; GCN: SI_RETURN_TO_EPILOG %1
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%0:sreg_32 = S_MOV_B32 2048
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%1.lo16:vgpr_32 = COPY killed %0.hi16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_simm_16_sub_to_sub_lo_to_hi
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body: |
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bb.0:
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; GCN-LABEL: name: fold_simm_16_sub_to_sub_lo_to_hi
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: %1.hi16:sreg_32 = COPY killed [[S_MOV_B32_]].lo16
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; GCN: SI_RETURN_TO_EPILOG %1
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%0:sreg_32 = S_MOV_B32 2048
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%1.hi16:sreg_32 = COPY killed %0.lo16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_simm_16_sub_to_sub_hi_to_lo_2048
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body: |
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bb.0:
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; GCN-LABEL: name: fold_simm_16_sub_to_sub_hi_to_lo_2048
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GCN: SI_RETURN_TO_EPILOG [[S_MOV_B32_1]]
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%0:sreg_32 = S_MOV_B32 2048
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%1.lo16:sreg_32 = COPY killed %0.hi16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_simm_16_sub_to_sub_hi_to_lo_shifted_2048
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body: |
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bb.0:
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; GCN-LABEL: name: fold_simm_16_sub_to_sub_hi_to_lo_shifted_2048
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 134217728
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; GCN: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: SI_RETURN_TO_EPILOG [[S_MOV_B32_1]]
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%0:sreg_32 = S_MOV_B32 134217728
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%1.lo16:sreg_32 = COPY killed %0.hi16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_aimm_16_sub_to_sub_hi_to_lo_2048
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body: |
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bb.0:
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; GCN-LABEL: name: fold_aimm_16_sub_to_sub_hi_to_lo_2048
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2048
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; GCN: [[V_ACCVGPR_WRITE_B32_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32 0, implicit $exec
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; GCN: SI_RETURN_TO_EPILOG [[V_ACCVGPR_WRITE_B32_]]
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%0:sreg_32 = S_MOV_B32 2048
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%1.lo16:agpr_32 = COPY killed %0.hi16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_aimm_16_sub_to_sub_hi_to_lo_shifted_1
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body: |
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bb.0:
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; GCN-LABEL: name: fold_aimm_16_sub_to_sub_hi_to_lo_shifted_1
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65536
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; GCN: [[V_ACCVGPR_WRITE_B32_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32 1, implicit $exec
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; GCN: SI_RETURN_TO_EPILOG [[V_ACCVGPR_WRITE_B32_]]
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%0:sreg_32 = S_MOV_B32 65536
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%1.lo16:agpr_32 = COPY killed %0.hi16
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SI_RETURN_TO_EPILOG %1
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...
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---
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name: fold_aimm_16_sub_to_sub_hi_to_lo_shifted_2048
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body: |
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bb.0:
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; GCN-LABEL: name: fold_aimm_16_sub_to_sub_hi_to_lo_shifted_2048
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 134217728
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; GCN: %1.lo16:agpr_32 = COPY killed [[S_MOV_B32_]].hi16
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; GCN: SI_RETURN_TO_EPILOG %1
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%0:sreg_32 = S_MOV_B32 134217728
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%1.lo16:agpr_32 = COPY killed %0.hi16
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SI_RETURN_TO_EPILOG %1
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...
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