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[RISCV] Prevent bad legalizer behavior when bitcasting fixed vectors to i64 on RV32 with Zve32. 

Similar to D113219, we need to make sure we don't create a vXi64
vector when it isn't legal. This fixes an error found by an
expensive checks build.
This commit is contained in:
Craig Topper 2021-11-10 11:54:10 -08:00
parent 18d883cc0a
commit 9ee5cec688
1 changed files with 6 additions and 4 deletions
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6
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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@ -5726,11 +5726,13 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
// scalar types in order to improve codegen. Bitcast the vector to a
// one-element vector type whose element type is the same as the result
// type, and extract the first element.
LLVMContext &Context = *DAG.getContext();
SDValue BVec = DAG.getBitcast(EVT::getVectorVT(Context, VT, 1), Op0);
EVT BVT = EVT::getVectorVT(*DAG.getContext(), VT, 1);
if (isTypeLegal(BVT)) {
SDValue BVec = DAG.getBitcast(BVT, Op0);
Results.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, BVec,
DAG.getConstant(0, DL, XLenVT)));
}
}
break;
}
case RISCVISD::GREV: