From 9ee5cec688add4c0589a8ff08f49e274fa6d45a2 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 10 Nov 2021 11:54:10 -0800 Subject: [PATCH] [RISCV] Prevent bad legalizer behavior when bitcasting fixed vectors to i64 on RV32 with Zve32. Similar to D113219, we need to make sure we don't create a vXi64 vector when it isn't legal. This fixes an error found by an expensive checks build. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index c948bdecf14a..4ab8e2e3f4bb 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -5726,10 +5726,12 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, // scalar types in order to improve codegen. Bitcast the vector to a // one-element vector type whose element type is the same as the result // type, and extract the first element. - LLVMContext &Context = *DAG.getContext(); - SDValue BVec = DAG.getBitcast(EVT::getVectorVT(Context, VT, 1), Op0); - Results.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, BVec, - DAG.getConstant(0, DL, XLenVT))); + EVT BVT = EVT::getVectorVT(*DAG.getContext(), VT, 1); + if (isTypeLegal(BVT)) { + SDValue BVec = DAG.getBitcast(BVT, Op0); + Results.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, BVec, + DAG.getConstant(0, DL, XLenVT))); + } } break; }