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fix obviously bogus (IMO) operand index of the load in asserts 

(load only has one operand) and smuggle in some whitespace changes too

NB: I am obviously testing the water here, and believe that the unguarded
    cast is still wrong, but why is the getZExtValue of the load's operand
    tested against zero here? Any review is appreciated.
llvm-svn: 155190
This commit is contained in:
Gabor Greif 2012-04-20 08:58:49 +00:00
parent f32a377a7c
commit 9eccbe9c82
1 changed files with 3 additions and 3 deletions
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6
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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@ -902,7 +902,7 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
return true; // [r+i] return true; // [r+i]
} else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
// Match LOAD (ADD (X, Lo(G))). // Match LOAD (ADD (X, Lo(G))).
assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(0))->getZExtValue()
&& "Cannot handle constant offsets yet!"); && "Cannot handle constant offsets yet!");
Disp = N.getOperand(1).getOperand(0); // The global address. Disp = N.getOperand(1).getOperand(0); // The global address.
assert(Disp.getOpcode() == ISD::TargetGlobalAddress || assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
@ -1006,7 +1006,7 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
if (N.getOpcode() == ISD::ADD) { if (N.getOpcode() == ISD::ADD) {
short imm = 0; short imm = 0;
if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
} else { } else {
@ -1015,7 +1015,7 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
return true; // [r+i] return true; // [r+i]
} else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
// Match LOAD (ADD (X, Lo(G))). // Match LOAD (ADD (X, Lo(G))).
assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(0))->getZExtValue()
&& "Cannot handle constant offsets yet!"); && "Cannot handle constant offsets yet!");
Disp = N.getOperand(1).getOperand(0); // The global address. Disp = N.getOperand(1).getOperand(0); // The global address.
assert(Disp.getOpcode() == ISD::TargetGlobalAddress || assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||