[llvm-mca] Minor style changes. NFC

llvm-svn: 339823

llvm/tools/llvm-mca/DispatchStage.h

@@ -49,7 +49,7 @@ class Scheduler;
 //
 // If the number of micro opcodes exceedes DispatchWidth, then the instruction
 // is dispatched in multiple cycles.
-class DispatchStage : public Stage {
+class DispatchStage final : public Stage {
   unsigned DispatchWidth;
   unsigned AvailableEntries;
   unsigned CarryOver;
@@ -92,9 +92,9 @@ public:
   // We can always try to dispatch, so returning false is okay in this case.
   // The retire stage, which controls the RCU, might have items to complete but
   // RetireStage::hasWorkToComplete will check for that case.
-  virtual bool hasWorkToComplete() const override final { return false; }
-  virtual void cycleStart() override final;
-  virtual Status execute(InstRef &IR) override final;
+  bool hasWorkToComplete() const override { return false; }
+  void cycleStart() override;
+  Status execute(InstRef &IR) override;
   void notifyDispatchStall(const InstRef &IR, unsigned EventType);
 
 #ifndef NDEBUG

llvm/tools/llvm-mca/ExecuteStage.h

@@ -8,7 +8,7 @@
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file defines the execution stage of an instruction pipeline.
+/// This file defines the execution stage of a default instruction pipeline.
 ///
 /// The ExecuteStage is responsible for managing the hardware scheduler
 /// and issuing notifications that an instruction has been executed.
@@ -26,7 +26,7 @@
 
 namespace mca {
 
-class ExecuteStage : public Stage {
+class ExecuteStage final : public Stage {
   // Owner will go away when we move listeners/eventing to the stages.
   RetireControlUnit &RCU;
   Scheduler &HWS;
@@ -36,17 +36,18 @@ class ExecuteStage : public Stage {
   void updateSchedulerQueues();
   void issueReadyInstructions();
 
-public:
-  ExecuteStage(RetireControlUnit &R, Scheduler &S) : Stage(), RCU(R), HWS(S) {}
   ExecuteStage(const ExecuteStage &Other) = delete;
   ExecuteStage &operator=(const ExecuteStage &Other) = delete;
 
+public:
+  ExecuteStage(RetireControlUnit &R, Scheduler &S) : Stage(), RCU(R), HWS(S) {}
+
   // The ExecuteStage will always complete all of its work per call to
   // execute(), so it is never left in a 'to-be-processed' state.
-  virtual bool hasWorkToComplete() const override final { return false; }
+  bool hasWorkToComplete() const override { return false; }
 
-  virtual void cycleStart() override final;
-  virtual Status execute(InstRef &IR) override final;
+  void cycleStart() override;
+  Status execute(InstRef &IR) override;
 
   void
   notifyInstructionIssued(const InstRef &IR,

llvm/tools/llvm-mca/FetchStage.h

@@ -23,21 +23,22 @@
 
 namespace mca {
 
-class FetchStage : public Stage {
+class FetchStage final : public Stage {
   using InstMap = std::map<unsigned, std::unique_ptr<Instruction>>;
   InstMap Instructions;
   InstrBuilder &IB;
   SourceMgr &SM;
 
-public:
-  FetchStage(InstrBuilder &IB, SourceMgr &SM) : IB(IB), SM(SM) {}
   FetchStage(const FetchStage &Other) = delete;
   FetchStage &operator=(const FetchStage &Other) = delete;
 
-  bool hasWorkToComplete() const override final;
-  Status execute(InstRef &IR) override final;
-  void postExecute() override final;
-  void cycleEnd() override final;
+public:
+  FetchStage(InstrBuilder &IB, SourceMgr &SM) : IB(IB), SM(SM) {}
+
+  bool hasWorkToComplete() const override;
+  Status execute(InstRef &IR) override;
+  void postExecute() override;
+  void cycleEnd() override;
 };
 
 } // namespace mca

llvm/tools/llvm-mca/RetireStage.h

@@ -8,7 +8,7 @@
 //===----------------------------------------------------------------------===//
 /// \file
 ///
-/// This file defines the retire stage of an instruction pipeline.
+/// This file defines the retire stage of a default instruction pipeline.
 /// The RetireStage represents the process logic that interacts with the
 /// simulated RetireControlUnit hardware.
 //
@@ -23,22 +23,21 @@
 
 namespace mca {
 
-class RetireStage : public Stage {
+class RetireStage final : public Stage {
   // Owner will go away when we move listeners/eventing to the stages.
   RetireControlUnit &RCU;
   RegisterFile &PRF;
 
-public:
-  RetireStage(RetireControlUnit &R, RegisterFile &F)
-      : Stage(), RCU(R), PRF(F) {}
   RetireStage(const RetireStage &Other) = delete;
   RetireStage &operator=(const RetireStage &Other) = delete;
 
-  virtual bool hasWorkToComplete() const override final {
-    return !RCU.isEmpty();
-  }
-  virtual void cycleStart() override final;
-  virtual Status execute(InstRef &IR) override final { return Stage::Continue; }
+public:
+  RetireStage(RetireControlUnit &R, RegisterFile &F)
+      : Stage(), RCU(R), PRF(F) {}
+
+  bool hasWorkToComplete() const override { return !RCU.isEmpty(); }
+  void cycleStart() override;
+  Status execute(InstRef &IR) override { return Stage::Continue; }
   void notifyInstructionRetired(const InstRef &IR);
   void onInstructionExecuted(unsigned TokenID);
 };