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[X86][PCLMUL] Add scheduling latency/throughput test for PCLMULQDQ instruction 

Added it to the SSE42 tests as targets seem to always have both

llvm-svn: 311166
This commit is contained in:
Simon Pilgrim 2017-08-18 15:08:30 +00:00
parent 8d5b257d02
commit 9eb0869e91
1 changed files with 44 additions and 1 deletions
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45
llvm/test/CodeGen/X86/sse42-schedule.ll
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@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+sse4.2 | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+sse4.2,+pclmul | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=slm | FileCheck %s --check-prefix=CHECK --check-prefix=SLM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=sandybridge | FileCheck %s --check-prefix=CHECK --check-prefix=SANDY
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=ivybridge | FileCheck %s --check-prefix=CHECK --check-prefix=SANDY
@ -554,3 +554,46 @@ define <2 x i64> @test_pcmpgtq(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
%5 = sext <2 x i1> %4 to <2 x i64>
ret <2 x i64> %5
}
define <2 x i64> @test_pclmulqdq(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> *%a2) {
; GENERIC-LABEL: test_pclmulqdq:
; GENERIC: # BB#0:
; GENERIC-NEXT: pclmulqdq $0, %xmm1, %xmm0 # sched: [14:6.00]
; GENERIC-NEXT: pclmulqdq $0, (%rdi), %xmm0 # sched: [14:5.67]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SLM-LABEL: test_pclmulqdq:
; SLM: # BB#0:
; SLM-NEXT: pclmulqdq $0, %xmm1, %xmm0 # sched: [10:10.00]
; SLM-NEXT: pclmulqdq $0, (%rdi), %xmm0 # sched: [10:10.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
; SANDY-LABEL: test_pclmulqdq:
; SANDY: # BB#0:
; SANDY-NEXT: vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # sched: [14:6.00]
; SANDY-NEXT: vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [14:5.67]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_pclmulqdq:
; HASWELL: # BB#0:
; HASWELL-NEXT: vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # sched: [7:2.00]
; HASWELL-NEXT: vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [7:2.00]
; HASWELL-NEXT: retq # sched: [1:1.00]
;
; BTVER2-LABEL: test_pclmulqdq:
; BTVER2: # BB#0:
; BTVER2-NEXT: vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # sched: [2:1.00]
; BTVER2-NEXT: vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [7:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_pclmulqdq:
; ZNVER1: # BB#0:
; ZNVER1-NEXT: vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # sched: [100:?]
; ZNVER1-NEXT: vpclmulqdq $0, (%rdi), %xmm0, %xmm0 # sched: [100:?]
; ZNVER1-NEXT: retq # sched: [5:0.50]
%1 = load <2 x i64>, <2 x i64> *%a2, align 16
%2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a0, <2 x i64> %a1, i8 0)
%3 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %2, i8 0)
ret <2 x i64> %3
}
declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8)