forked from OSchip/llvm-project
[mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions
Differential Revision: http://reviews.llvm.org/D11801 llvm-svn: 246999
This commit is contained in:
Zoran Jovanovic
parent
e67a9d6d24
commit
9eaa30d2bf
|
|
@ -256,6 +256,11 @@ static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
|
|||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
|
||||
unsigned Insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeSyncI(MCInst &Inst,
|
||||
unsigned Insn,
|
||||
uint64_t Address,
|
||||
|
|
@ -1164,6 +1169,24 @@ static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
|
|||
return MCDisassembler::Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
|
||||
unsigned Insn,
|
||||
uint64_t Address,
|
||||
const void *Decoder) {
|
||||
int Offset = SignExtend32<9>(Insn & 0x1ff);
|
||||
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
|
||||
unsigned Base = fieldFromInstruction(Insn, 16, 5);
|
||||
|
||||
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
|
||||
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
|
||||
|
||||
Inst.addOperand(MCOperand::createReg(Reg));
|
||||
Inst.addOperand(MCOperand::createReg(Base));
|
||||
Inst.addOperand(MCOperand::createImm(Offset));
|
||||
|
||||
return MCDisassembler::Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSyncI(MCInst &Inst,
|
||||
unsigned Insn,
|
||||
uint64_t Address,
|
||||
|
|
|
|||
|
|
@ -769,6 +769,19 @@ getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
|
|||
return OffBits & 0x7F;
|
||||
}
|
||||
|
||||
unsigned MipsMCCodeEmitter::
|
||||
getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const {
|
||||
// Base register is encoded in bits 20-16, offset is encoded in bits 8-0.
|
||||
assert(MI.getOperand(OpNo).isReg());
|
||||
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
|
||||
STI) << 16;
|
||||
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
|
||||
|
||||
return (OffBits & 0x1FF) | RegBits;
|
||||
}
|
||||
|
||||
unsigned MipsMCCodeEmitter::
|
||||
getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
|
|
|
|||
|
|
@ -172,6 +172,9 @@ public:
|
|||
unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const;
|
||||
unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const;
|
||||
unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const;
|
||||
|
|
|
|||
|
|
@ -224,6 +224,36 @@ class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
|
|||
let Inst{5-0} = funct;
|
||||
}
|
||||
|
||||
class SB32_SH32_STORE_FM_MMR6<bits<6> op> {
|
||||
bits<5> rt;
|
||||
bits<21> addr;
|
||||
bits<5> base = addr{20-16};
|
||||
bits<16> offset = addr{15-0};
|
||||
|
||||
bits<32> Inst;
|
||||
|
||||
let Inst{31-26} = op;
|
||||
let Inst{25-21} = rt;
|
||||
let Inst{20-16} = base;
|
||||
let Inst{15-0} = offset;
|
||||
}
|
||||
|
||||
class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
|
||||
bits<5> rt;
|
||||
bits<21> addr;
|
||||
bits<5> base = addr{20-16};
|
||||
bits<9> offset = addr{8-0};
|
||||
|
||||
bits<32> Inst;
|
||||
|
||||
let Inst{31-26} = 0b011000;
|
||||
let Inst{25-21} = rt;
|
||||
let Inst{20-16} = base;
|
||||
let Inst{15-12} = 0b1010;
|
||||
let Inst{11-9} = funct;
|
||||
let Inst{8-0} = offset;
|
||||
}
|
||||
|
||||
class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
|
||||
bits<5> rt;
|
||||
bits<16> offset;
|
||||
|
|
|
|||
|
|
@ -11,6 +11,14 @@
|
|||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def mem_mm_9 : Operand<i32> {
|
||||
let PrintMethod = "printMemOperand";
|
||||
let MIOperandInfo = (ops GPR32, simm9);
|
||||
let EncoderMethod = "getMemEncodingMMImm9";
|
||||
let ParserMatchClass = MipsMemAsmOperand;
|
||||
let OperandType = "OPERAND_MEMORY";
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// Instruction Encodings
|
||||
|
|
@ -91,6 +99,11 @@ class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
|
|||
class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
|
||||
class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
|
||||
class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
|
||||
class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
|
||||
class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
|
||||
class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
|
||||
class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
|
||||
class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
|
||||
|
||||
class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
|
||||
RegisterOperand GPROpnd>
|
||||
|
|
@ -605,6 +618,25 @@ class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
|
|||
class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
|
||||
AFGR64Opnd, II_TRUNC>;
|
||||
|
||||
class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
|
||||
: Store<opstr, RO>, MMR6Arch<opstr> {
|
||||
let DecoderMethod = "DecodeMemMMImm16";
|
||||
}
|
||||
class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
|
||||
|
||||
class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
|
||||
: MMR6Arch<instr_asm>, MipsR6Inst {
|
||||
dag OutOperandList = (outs);
|
||||
dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
|
||||
string DecoderMethod = "DecodeStoreEvaOpMM";
|
||||
bit mayStore = 1;
|
||||
}
|
||||
class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
|
||||
class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
|
||||
class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
|
||||
class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// Instruction Definitions
|
||||
|
|
@ -788,6 +820,11 @@ def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
|
|||
ISA_MICROMIPS32R6;
|
||||
def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
|
||||
ISA_MICROMIPS32R6;
|
||||
def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
|
||||
def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
|
||||
def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
|
||||
def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
|
||||
def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -1228,7 +1228,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
|
|||
def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
|
||||
LW_FM<0x23>;
|
||||
}
|
||||
def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
|
||||
def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
|
||||
LW_FM<0x28>;
|
||||
def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
|
||||
|
|
@ -1646,7 +1647,7 @@ def : MipsInstAlias<"beqz $rs,$offset",
|
|||
def : MipsInstAlias<"beqzl $rs,$offset",
|
||||
(BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
|
||||
def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
|
||||
|
||||
|
||||
def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
|
||||
def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
|
|
|
|||
|
|
@ -132,6 +132,16 @@
|
|||
|
||||
0x70 0x64 0x04 0xd2 # CHECK: xori $3, $4, 1234
|
||||
|
||||
0x18 0x85 0x00 0x06 # CHECK: sb $4, 6($5)
|
||||
|
||||
0x60 0x85 0xa8 0x06 # CHECK: sbe $4, 6($5)
|
||||
|
||||
0x60 0x85 0xac 0x06 # CHECK: sce $4, 6($5)
|
||||
|
||||
0x38 0x85 0x00 0x06 # CHECK: sh $4, 6($5)
|
||||
|
||||
0x60 0x85 0xaa 0x06 # CHECK: she $4, 6($5)
|
||||
|
||||
0x00 0x64 0x2b 0x3c # CHECK: seb $3, $4
|
||||
|
||||
0x00 0x64 0x3b 0x3c # CHECK: seh $3, $4
|
||||
|
|
|
|||
|
|
@ -163,4 +163,9 @@
|
|||
lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82]
|
||||
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
|
||||
lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f]
|
||||
sb $4, 6($5) # CHECK: sb $4, 6($5) # encoding: [0x18,0x85,0x00,0x06]
|
||||
sbe $4, 6($5) # CHECK: sbe $4, 6($5) # encoding: [0x60,0x85,0xa8,0x06]
|
||||
sce $4, 6($5) # CHECK: sce $4, 6($5) # encoding: [0x60,0x85,0xac,0x06]
|
||||
sh $4, 6($5) # CHECK: sh $4, 6($5) # encoding: [0x38,0x85,0x00,0x06]
|
||||
she $4, 6($5) # CHECK: she $4, 6($5) # encoding: [0x60,0x85,0xaa,0x06]
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue