forked from OSchip/llvm-project
[RISCV] Remove unnecessary word from error message.
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@ -11636,7 +11636,7 @@ def warn_tcb_enforcement_violation : Warning<
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// RISC-V builtin required extension warning
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def err_riscv_builtin_requires_extension : Error<
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"builtin requires at least one of the following extensions support to be enabled : %0">;
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"builtin requires at least one of the following extensions to be enabled : %0">;
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def err_riscv_builtin_invalid_lmul : Error<
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"LMUL argument must be in the range [0,3] or [5,7]">;
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@ -2,5 +2,5 @@
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// RUN: %clang_cc1 -triple riscv32 -target-feature +zbb -verify %s -o -
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int orc_b_64(int a) {
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return __builtin_riscv_orc_b_64(a); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'RV64'}}
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return __builtin_riscv_orc_b_64(a); // expected-error {{builtin requires at least one of the following extensions to be enabled : 'RV64'}}
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}
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@ -3,10 +3,10 @@
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int zip(int rs1)
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{
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return __builtin_riscv_zip_32(rs1); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'RV32'}}
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return __builtin_riscv_zip_32(rs1); // expected-error {{builtin requires at least one of the following extensions to be enabled : 'RV32'}}
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}
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int unzip(int rs1)
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{
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return __builtin_riscv_unzip_32(rs1); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'RV32'}}
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return __builtin_riscv_unzip_32(rs1); // expected-error {{builtin requires at least one of the following extensions to be enabled : 'RV32'}}
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}
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@ -11,7 +11,7 @@
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// CHECK-RV64V-NEXT: ret i32 [[CONV]]
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//
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// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions support to be enabled : 'Zve32x'
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// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions to be enabled : 'Zve32x'
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int test() {
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return __builtin_rvv_vsetvli(1, 0, 0);
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