forked from OSchip/llvm-project
[X86] Teach selectScalarSSELoad to not narrow volatile loads.
llvm-svn: 364498
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9f69052394
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@ -2283,12 +2283,14 @@ bool X86DAGToDAGISel::selectScalarSSELoad(SDNode *Root, SDNode *Parent,
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if (!hasSingleUsesFromRoot(Root, Parent))
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return false;
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// We can allow a full vector load here since narrowing a load is ok.
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// We can allow a full vector load here since narrowing a load is ok unless
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// it's volatile.
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if (ISD::isNON_EXTLoad(N.getNode())) {
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PatternNodeWithChain = N;
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if (IsProfitableToFold(PatternNodeWithChain, N.getNode(), Root) &&
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IsLegalToFold(PatternNodeWithChain, Parent, Root, OptLevel)) {
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LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
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LoadSDNode *LD = cast<LoadSDNode>(N);
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if (!LD->isVolatile() &&
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IsProfitableToFold(N, LD, Root) &&
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IsLegalToFold(N, Parent, Root, OptLevel)) {
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PatternNodeWithChain = N;
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return selectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp,
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Segment);
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}
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@ -179,6 +179,23 @@ define <4 x float> @sqrtss_full_size(<4 x float>* %a) optsize{
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ret <4 x float> %res
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}
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define <4 x float> @sqrtss_full_size_volatile(<4 x float>* %a) optsize{
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; SSE-LABEL: sqrtss_full_size_volatile:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps (%rdi), %xmm0
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; SSE-NEXT: sqrtss %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sqrtss_full_size_volatile:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps (%rdi), %xmm0
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; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%ld = load volatile <4 x float>, <4 x float>* %a
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%res = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %ld)
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ret <4 x float> %res
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}
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define double @sqrtsd_size(double* %a) optsize {
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; SSE-LABEL: sqrtsd_size:
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; SSE: # %bb.0:
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@ -213,6 +230,23 @@ define <2 x double> @sqrtsd_full_size(<2 x double>* %a) optsize {
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ret <2 x double> %res
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}
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define <2 x double> @sqrtsd_full_size_volatile(<2 x double>* %a) optsize {
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; SSE-LABEL: sqrtsd_full_size_volatile:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd (%rdi), %xmm0
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; SSE-NEXT: sqrtsd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sqrtsd_full_size_volatile:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovapd (%rdi), %xmm0
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; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%ld = load volatile <2 x double>, <2 x double>* %a
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%res = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %ld)
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ret <2 x double> %res
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}
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declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
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declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
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