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[X86][Znver1] Fix instregex entries that don't match any instructions (D44687) 

Reviewed by @GGanesh and @craig.topper

llvm-svn: 328309
This commit is contained in:
Simon Pilgrim 2018-03-23 12:08:23 +00:00
parent 2755893834
commit 9ea14bbbb0
1 changed files with 3 additions and 4 deletions
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7
llvm/lib/Target/X86/X86ScheduleZnver1.td
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@ -367,8 +367,7 @@ def : InstRW<[WriteALULd],
// INC DEC NOT NEG.
// m.
def : InstRW<[WriteALULd],
(instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m",
"(INC|DEC)64(16|32)m")>;
(instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m")>;
// MUL IMUL.
// r16.
@ -499,7 +498,7 @@ def ZnWriteRET : SchedWriteRes<[ZnALU03]> {
let NumMicroOps = 2;
}
def : InstRW<[ZnWriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)",
"IRET(D|Q)", "RETF")>;
"IRET(16|32|64)")>;
//-- Logic instructions --//
@ -913,7 +912,7 @@ def : InstRW<[ZnWriteFPU2], (instregex "MMX_MOVD64rr", "MMX_MOVD64to64rr",
def : InstRW<[ZnWriteToALU2], (instregex "VMOVPQIto64rr")>;
// (x)mm <- r64.
def : InstRW<[ZnWriteFPU2], (instregex "VMOV64toPQIrr", "VMOVZQI2PQIrr")>;
def : InstRW<[ZnWriteFPU2], (instregex "VMOV64toPQIrr")>;
// (x)mm <- (x)mm.
def : InstRW<[ZnWriteFPU], (instregex "MMX_MOVQ64rr")>;