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[mips] Refactor logical NOR instructions. 

llvm-svn: 170937
This commit is contained in:
Akira Hatanaka 2012-12-21 22:35:47 +00:00
parent ac10697207
commit 9e89195dce
2 changed files with 6 additions and 7 deletions
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2
llvm/lib/Target/Mips/Mips64InstrInfo.td
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@ -105,7 +105,7 @@ def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
def AND64 : ArithLogicR<"and", CPU64Regs, 1, IIAlu, and>, ADD_FM<0, 0x24>;
def OR64 : ArithLogicR<"or", CPU64Regs, 1, IIAlu, or>, ADD_FM<0, 0x25>;
def XOR64 : ArithLogicR<"xor", CPU64Regs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
def NOR64 : LogicNOR<"nor", CPU64Regs>, ADD_FM<0, 0x27>;
/// Shift Instructions
def DSLL : shift_rotate_imm64<"dsll", shl>, SRA_FM<0x38, 0>;

11
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -364,11 +364,10 @@ class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
}
// Logical
class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
!strconcat(instr_asm, "\t$rd, $rs, $rt"),
[(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
let shamt = 0;
class LogicNOR<string opstr, RegisterClass RC>:
InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
!strconcat(opstr, "\t$rd, $rs, $rt"),
[(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> {
let isCommutable = 1;
}
@ -881,7 +880,7 @@ def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>;
def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>;
def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
def NOR : LogicNOR<"nor", CPURegs>, ADD_FM<0, 0x27>;
/// Shift Instructions
def SLL : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>;