forked from OSchip/llvm-project
AMDGPU/GlobalISel: Fix RegBankSelect for GEP.
This is basically a pointer typed add, so shouldn't be any different. This was assuming everything was an SGPR, which is not true. Also cleanup legality for GEP. I don't seem to be seeing the problem the hack marking s64 as a legal pointer type the comment mentions. llvm-svn: 354067
This commit is contained in:
Matt Arsenault
parent
871821f786
commit
9e5e868d95
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@ -115,12 +115,12 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
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const LLT CodePtr = FlatPtr;
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const LLT AddrSpaces[] = {
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GlobalPtr,
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ConstantPtr,
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LocalPtr,
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FlatPtr,
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PrivatePtr
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const std::initializer_list<LLT> AddrSpaces64 = {
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GlobalPtr, ConstantPtr, FlatPtr
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};
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const std::initializer_list<LLT> AddrSpaces32 = {
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LocalPtr, PrivatePtr
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};
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setAction({G_BRCOND, S1}, Legal);
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@ -245,19 +245,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
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.legalFor({S32, S64})
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.scalarize(0);
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for (LLT PtrTy : AddrSpaces) {
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LLT IdxTy = LLT::scalar(PtrTy.getSizeInBits());
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setAction({G_GEP, PtrTy}, Legal);
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setAction({G_GEP, 1, IdxTy}, Legal);
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}
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// FIXME: When RegBankSelect inserts copies, it will only create new registers
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// with scalar types. This means we can end up with G_LOAD/G_STORE/G_GEP
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// instruction with scalar types for their pointer operands. In assert builds,
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// the instruction selector will assert if it sees a generic instruction which
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// isn't legal, so we need to tell it that scalar types are legal for pointer
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// operands
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setAction({G_GEP, S64}, Legal);
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getActionDefinitionsBuilder(G_GEP)
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.legalForCartesianProduct(AddrSpaces64, {S64})
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.legalForCartesianProduct(AddrSpaces32, {S32})
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.scalarize(0);
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setAction({G_BLOCK_ADDR, CodePtr}, Legal);
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@ -314,8 +306,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
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getActionDefinitionsBuilder(G_INTTOPTR)
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// List the common cases
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.legalForCartesianProduct({GlobalPtr, ConstantPtr, FlatPtr}, {S64})
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.legalForCartesianProduct({LocalPtr, PrivatePtr}, {S32})
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.legalForCartesianProduct(AddrSpaces64, {S64})
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.legalForCartesianProduct(AddrSpaces32, {S32})
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.scalarize(0)
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// Accept any address space as long as the size matches
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.legalIf(sameSize(0, 1))
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@ -330,8 +322,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
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getActionDefinitionsBuilder(G_PTRTOINT)
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// List the common cases
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.legalForCartesianProduct({GlobalPtr, ConstantPtr, FlatPtr}, {S64})
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.legalForCartesianProduct({LocalPtr, PrivatePtr}, {S32})
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.legalForCartesianProduct(AddrSpaces64, {S64})
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.legalForCartesianProduct(AddrSpaces32, {S32})
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.scalarize(0)
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// Accept any address space as long as the size matches
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.legalIf(sameSize(0, 1))
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@ -605,6 +605,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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LLVM_FALLTHROUGH;
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}
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case AMDGPU::G_GEP:
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case AMDGPU::G_ADD:
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case AMDGPU::G_SUB:
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case AMDGPU::G_MUL:
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@ -744,16 +745,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
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break;
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}
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case AMDGPU::G_GEP: {
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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if (!MI.getOperand(i).isReg())
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continue;
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unsigned Size = MRI.getType(MI.getOperand(i).getReg()).getSizeInBits();
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OpdsMapping[i] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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}
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break;
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}
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case AMDGPU::G_STORE: {
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assert(MI.getOperand(0).isReg());
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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@ -0,0 +1,90 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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---
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name: gep_p1_s_k
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: gep_p1_s_k
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; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
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; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 1
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; CHECK: [[GEP:%[0-9]+]]:sgpr(p1) = G_GEP [[COPY]], [[C]](s64)
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%0:_(p1) = COPY $sgpr0_sgpr1
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(p1) = G_GEP %0, %1
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...
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---
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name: gep_p1_s_s
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
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; CHECK-LABEL: name: gep_p1_s_s
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; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
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; CHECK: [[GEP:%[0-9]+]]:sgpr(p1) = G_GEP [[COPY]], [[COPY1]](s64)
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%0:_(p1) = COPY $sgpr0_sgpr1
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%1:_(s64) = COPY $sgpr2_sgpr3
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%2:_(p1) = G_GEP %0, %1
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...
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---
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name: gep_p1_v_k
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: gep_p1_v_k
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; CHECK: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
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; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 1
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64)
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; CHECK: [[GEP:%[0-9]+]]:vgpr(p1) = G_GEP [[COPY]], [[COPY1]](s64)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_CONSTANT i64 1
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%2:_(p1) = G_GEP %0, %1
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...
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---
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name: gep_p1_v_s
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
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; CHECK-LABEL: name: gep_p1_v_s
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; CHECK: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
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; CHECK: [[GEP:%[0-9]+]]:vgpr(p1) = G_GEP [[COPY]], [[COPY2]](s64)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s64) = COPY $sgpr0_sgpr1
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%2:_(p1) = G_GEP %0, %1
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...
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---
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name: gep_p1_v_v
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; CHECK-LABEL: name: gep_p1_v_v
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; CHECK: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
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; CHECK: [[GEP:%[0-9]+]]:vgpr(p1) = G_GEP [[COPY]], [[COPY1]](s64)
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%0:_(p1) = COPY $vgpr0_vgpr1
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%1:_(s64) = COPY $vgpr2_vgpr3
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%2:_(p1) = G_GEP %0, %1
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...
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