forked from OSchip/llvm-project
Akira Hatanaka
parent
314b43b781
commit
9e4e5a87c4
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@ -596,3 +596,223 @@ entry:
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}
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declare i32 @llvm.mips.muleq.s.w.phr(<2 x i16>, <2 x i16>) nounwind
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define { i32 } @test__builtin_mips_precrq_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
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entry:
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; CHECK: precrq.qb.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = tail call <4 x i8> @llvm.mips.precrq.qb.ph(<2 x i16> %0, <2 x i16> %1)
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%3 = bitcast <4 x i8> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <4 x i8> @llvm.mips.precrq.qb.ph(<2 x i16>, <2 x i16>) nounwind readnone
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define { i32 } @test__builtin_mips_precrq_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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; CHECK: precrq.ph.w
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%0 = tail call <2 x i16> @llvm.mips.precrq.ph.w(i32 %a0, i32 %a1)
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%1 = bitcast <2 x i16> %0 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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declare <2 x i16> @llvm.mips.precrq.ph.w(i32, i32) nounwind readnone
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define { i32 } @test__builtin_mips_precrq_rs_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {
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entry:
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; CHECK: precrq_rs.ph.w
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%0 = tail call <2 x i16> @llvm.mips.precrq.rs.ph.w(i32 %a0, i32 %a1)
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%1 = bitcast <2 x i16> %0 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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declare <2 x i16> @llvm.mips.precrq.rs.ph.w(i32, i32) nounwind
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define { i32 } @test__builtin_mips_precrqu_s_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: precrqu_s.qb.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = tail call <4 x i8> @llvm.mips.precrqu.s.qb.ph(<2 x i16> %0, <2 x i16> %1)
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%3 = bitcast <4 x i8> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <4 x i8> @llvm.mips.precrqu.s.qb.ph(<2 x i16>, <2 x i16>) nounwind
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define i32 @test__builtin_mips_cmpu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: cmpu.eq.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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tail call void @llvm.mips.cmpu.eq.qb(<4 x i8> %0, <4 x i8> %1)
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%2 = tail call i32 @llvm.mips.rddsp(i32 31)
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ret i32 %2
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}
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declare void @llvm.mips.cmpu.eq.qb(<4 x i8>, <4 x i8>) nounwind
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declare i32 @llvm.mips.rddsp(i32) nounwind readonly
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define i32 @test__builtin_mips_cmpu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: cmpu.lt.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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tail call void @llvm.mips.cmpu.lt.qb(<4 x i8> %0, <4 x i8> %1)
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%2 = tail call i32 @llvm.mips.rddsp(i32 31)
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ret i32 %2
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}
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declare void @llvm.mips.cmpu.lt.qb(<4 x i8>, <4 x i8>) nounwind
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define i32 @test__builtin_mips_cmpu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: cmpu.le.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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tail call void @llvm.mips.cmpu.le.qb(<4 x i8> %0, <4 x i8> %1)
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%2 = tail call i32 @llvm.mips.rddsp(i32 31)
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ret i32 %2
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}
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declare void @llvm.mips.cmpu.le.qb(<4 x i8>, <4 x i8>) nounwind
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define i32 @test__builtin_mips_cmpgu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: cmpgu.eq.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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%2 = tail call i32 @llvm.mips.cmpgu.eq.qb(<4 x i8> %0, <4 x i8> %1)
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ret i32 %2
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}
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declare i32 @llvm.mips.cmpgu.eq.qb(<4 x i8>, <4 x i8>) nounwind
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define i32 @test__builtin_mips_cmpgu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: cmpgu.lt.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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%2 = tail call i32 @llvm.mips.cmpgu.lt.qb(<4 x i8> %0, <4 x i8> %1)
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ret i32 %2
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}
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declare i32 @llvm.mips.cmpgu.lt.qb(<4 x i8>, <4 x i8>) nounwind
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define i32 @test__builtin_mips_cmpgu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: cmpgu.le.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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%2 = tail call i32 @llvm.mips.cmpgu.le.qb(<4 x i8> %0, <4 x i8> %1)
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ret i32 %2
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}
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declare i32 @llvm.mips.cmpgu.le.qb(<4 x i8>, <4 x i8>) nounwind
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define i32 @test__builtin_mips_cmp_eq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: cmp.eq.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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tail call void @llvm.mips.cmp.eq.ph(<2 x i16> %0, <2 x i16> %1)
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%2 = tail call i32 @llvm.mips.rddsp(i32 31)
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ret i32 %2
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}
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declare void @llvm.mips.cmp.eq.ph(<2 x i16>, <2 x i16>) nounwind
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define i32 @test__builtin_mips_cmp_lt_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: cmp.lt.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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tail call void @llvm.mips.cmp.lt.ph(<2 x i16> %0, <2 x i16> %1)
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%2 = tail call i32 @llvm.mips.rddsp(i32 31)
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ret i32 %2
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}
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declare void @llvm.mips.cmp.lt.ph(<2 x i16>, <2 x i16>) nounwind
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define i32 @test__builtin_mips_cmp_le_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: cmp.le.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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tail call void @llvm.mips.cmp.le.ph(<2 x i16> %0, <2 x i16> %1)
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%2 = tail call i32 @llvm.mips.rddsp(i32 31)
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ret i32 %2
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}
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declare void @llvm.mips.cmp.le.ph(<2 x i16>, <2 x i16>) nounwind
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define { i32 } @test__builtin_mips_pick_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readonly {
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entry:
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; CHECK: pick.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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%2 = tail call <4 x i8> @llvm.mips.pick.qb(<4 x i8> %0, <4 x i8> %1)
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%3 = bitcast <4 x i8> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <4 x i8> @llvm.mips.pick.qb(<4 x i8>, <4 x i8>) nounwind readonly
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define { i32 } @test__builtin_mips_pick_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readonly {
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entry:
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; CHECK: pick.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = tail call <2 x i16> @llvm.mips.pick.ph(<2 x i16> %0, <2 x i16> %1)
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%3 = bitcast <2 x i16> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <2 x i16> @llvm.mips.pick.ph(<2 x i16>, <2 x i16>) nounwind readonly
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define { i32 } @test__builtin_mips_packrl_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
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entry:
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; CHECK: packrl.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = tail call <2 x i16> @llvm.mips.packrl.ph(<2 x i16> %0, <2 x i16> %1)
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%3 = bitcast <2 x i16> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <2 x i16> @llvm.mips.packrl.ph(<2 x i16>, <2 x i16>) nounwind readnone
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define i32 @test__builtin_mips_rddsp1(i32 %i0) nounwind readonly {
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entry:
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; CHECK: rddsp
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%0 = tail call i32 @llvm.mips.rddsp(i32 31)
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ret i32 %0
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}
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@ -177,3 +177,77 @@ entry:
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}
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declare <2 x i16> @llvm.mips.subu.s.ph(<2 x i16>, <2 x i16>) nounwind
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define i32 @test__builtin_mips_cmpgdu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: cmpgdu.eq.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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%2 = tail call i32 @llvm.mips.cmpgdu.eq.qb(<4 x i8> %0, <4 x i8> %1)
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ret i32 %2
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}
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declare i32 @llvm.mips.cmpgdu.eq.qb(<4 x i8>, <4 x i8>) nounwind
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define i32 @test__builtin_mips_cmpgdu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: cmpgdu.lt.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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%2 = tail call i32 @llvm.mips.cmpgdu.lt.qb(<4 x i8> %0, <4 x i8> %1)
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ret i32 %2
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}
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declare i32 @llvm.mips.cmpgdu.lt.qb(<4 x i8>, <4 x i8>) nounwind
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define i32 @test__builtin_mips_cmpgdu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: cmpgdu.le.qb
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%1 = bitcast i32 %a1.coerce to <4 x i8>
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%2 = tail call i32 @llvm.mips.cmpgdu.le.qb(<4 x i8> %0, <4 x i8> %1)
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ret i32 %2
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}
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declare i32 @llvm.mips.cmpgdu.le.qb(<4 x i8>, <4 x i8>) nounwind
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define { i32 } @test__builtin_mips_precr_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
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entry:
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; CHECK: precr.qb.ph
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%1 = bitcast i32 %a1.coerce to <2 x i16>
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%2 = tail call <4 x i8> @llvm.mips.precr.qb.ph(<2 x i16> %0, <2 x i16> %1)
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%3 = bitcast <4 x i8> %2 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0
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ret { i32 } %.fca.0.insert
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}
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declare <4 x i8> @llvm.mips.precr.qb.ph(<2 x i16>, <2 x i16>) nounwind
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define { i32 } @test__builtin_mips_precr_sra_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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; CHECK: precr_sra.ph.w
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%0 = tail call <2 x i16> @llvm.mips.precr.sra.ph.w(i32 %a0, i32 %a1, i32 15)
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%1 = bitcast <2 x i16> %0 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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declare <2 x i16> @llvm.mips.precr.sra.ph.w(i32, i32, i32) nounwind readnone
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define { i32 } @test__builtin_mips_precr_sra_r_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
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entry:
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; CHECK: precr_sra_r.ph.w
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%0 = tail call <2 x i16> @llvm.mips.precr.sra.r.ph.w(i32 %a0, i32 %a1, i32 15)
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%1 = bitcast <2 x i16> %0 to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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declare <2 x i16> @llvm.mips.precr.sra.r.ph.w(i32, i32, i32) nounwind readnone
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