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[InstCombine] Allow fake vector insert folding to bit-logic only if the insert element is integer type 

The below commit is causing assertion when insert element type is not integer
 type such as half. This is because the transformation is creating zext before
 doing bitwise OR, and the zext is supported only for integer types
80ab06c599

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D114734
This commit is contained in:
Srividya Karumuri 2021-11-29 16:25:21 -08:00 committed by Daniel Sanders
parent 7e6df41f65
commit 9e3e1aad31
2 changed files with 24 additions and 1 deletions
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2
llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
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@ -2771,7 +2771,7 @@ Instruction *InstCombinerImpl::visitBitCast(BitCastInst &CI) {
if (match(Src, m_OneUse(m_InsertElt(m_OneUse(m_BitCast(m_Value(X))), if (match(Src, m_OneUse(m_InsertElt(m_OneUse(m_BitCast(m_Value(X))),
m_Value(Y), m_ConstantInt(IndexC)))) && m_Value(Y), m_ConstantInt(IndexC)))) &&
DestTy->isIntegerTy() && X->getType() == DestTy && DestTy->isIntegerTy() && X->getType() == DestTy &&
isDesirableIntType(BitWidth)) { Y->getType()->isIntegerTy() && isDesirableIntType(BitWidth)) {
// Adjust for big endian - the LSBs are at the high index. // Adjust for big endian - the LSBs are at the high index.
if (DL.isBigEndian()) if (DL.isBigEndian())
IndexC = SrcVTy->getNumElements() - 1 - IndexC; IndexC = SrcVTy->getNumElements() - 1 - IndexC;

23
llvm/test/Transforms/InstCombine/bitcast-inselt-bitcast.ll
View File

@ -70,6 +70,29 @@ define i32 @insert0_v4i8(i32 %x, i8 %y) {
ret i32 %r ret i32 %r
} }
; i32 is a common type, so we can convert independently of the data layout.
; Endian determines if a shift is needed (and so the transform is avoided).
; half type can not be used in zext instruction (and so the transform is avoided).
define i32 @insert0_v2half(i32 %x, half %y) {
; BE-LABEL: @insert0_v2half(
; BE-NEXT: [[V:%.*]] = bitcast i32 [[X:%.*]] to <2 x half>
; BE-NEXT: [[I:%.*]] = insertelement <2 x half> [[V]], half [[Y:%.*]], i8 0
; BE-NEXT: [[R:%.*]] = bitcast <2 x half> [[I]] to i32
; BE-NEXT: ret i32 [[R]]
;
; LE-LABEL: @insert0_v2half(
; LE-NEXT: [[V:%.*]] = bitcast i32 [[X:%.*]] to <2 x half>
; LE-NEXT: [[I:%.*]] = insertelement <2 x half> [[V]], half [[Y:%.*]], i8 0
; LE-NEXT: [[R:%.*]] = bitcast <2 x half> [[I]] to i32
; LE-NEXT: ret i32 [[R]]
;
%v = bitcast i32 %x to <2 x half>
%i = insertelement <2 x half> %v, half %y, i8 0
%r = bitcast <2 x half> %i to i32
ret i32 %r
}
; i64 is a legal type, so we can convert based on the data layout. ; i64 is a legal type, so we can convert based on the data layout.
; Endian determines if a shift is needed (and so the transform is avoided). ; Endian determines if a shift is needed (and so the transform is avoided).