- Use xor to clear integer registers (set R, 0).

- Added a new format for instructions where the source register is implied
  and it is same as the destination register. Used for pseudo instructions
  that clear the destination register.

llvm-svn: 25872

llvm/lib/Target/X86/X86.td

@@ -110,11 +110,11 @@ def X86InstrInfo : InstrInfo {
                        "FPFormBits",
                        "Opcode"];
   let TSFlagsShifts = [0,
-                       5,
                        6,
-                       10,
-                       12,
-                       16];
+                       7,
+                       11,
+                       13,
+                       17];
 }
 
 // The X86 target supports two different syntaxes for emitting machine code.

llvm/lib/Target/X86/X86CodeEmitter.cpp

@@ -473,7 +473,6 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
 
   case X86II::MRMSrcReg:
     MCE.emitByte(BaseOpcode);
-
     emitRegModRMByte(MI.getOperand(1).getReg(),
                      getX86RegNum(MI.getOperand(0).getReg()));
     if (MI.getNumOperands() == 3)
@@ -518,5 +517,11 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
         assert(0 && "Unknown operand!");
     }
     break;
+
+  case X86II::MRMInitReg:
+    MCE.emitByte(BaseOpcode);
+    emitRegModRMByte(MI.getOperand(0).getReg(),
+                     getX86RegNum(MI.getOperand(0).getReg()));
+    break;
   }
 }

llvm/lib/Target/X86/X86InstrInfo.h

@@ -75,7 +75,11 @@ namespace X86II {
     MRM0m = 24,  MRM1m = 25,  MRM2m = 26,  MRM3m = 27, // Format /0 /1 /2 /3
     MRM4m = 28,  MRM5m = 29,  MRM6m = 30,  MRM7m = 31, // Format /4 /5 /6 /7
 
-    FormMask       = 31,
+    // MRMInitReg - This form is used for instructions whose source and
+    // destinations are the same register.
+    MRMInitReg = 32,
+
+    FormMask       = 63,
 
     //===------------------------------------------------------------------===//
     // Actual flags...
@@ -83,14 +87,14 @@ namespace X86II {
     // OpSize - Set if this instruction requires an operand size prefix (0x66),
     // which most often indicates that the instruction operates on 16 bit data
     // instead of 32 bit data.
-    OpSize      = 1 << 5,
+    OpSize      = 1 << 6,
 
     // Op0Mask - There are several prefix bytes that are used to form two byte
     // opcodes.  These are currently 0x0F, 0xF3, and 0xD8-0xDF.  This mask is
     // used to obtain the setting of this field.  If no bits in this field is
     // set, there is no prefix byte for obtaining a multibyte opcode.
     //
-    Op0Shift    = 6,
+    Op0Shift    = 7,
     Op0Mask     = 0xF << Op0Shift,
 
     // TB - TwoByte - Set if this instruction has a two byte opcode, which
@@ -115,7 +119,7 @@ namespace X86II {
     //===------------------------------------------------------------------===//
     // This two-bit field describes the size of an immediate operand.  Zero is
     // unused so that we can tell if we forgot to set a value.
-    ImmShift = 10,
+    ImmShift = 11,
     ImmMask  = 7 << ImmShift,
     Imm8     = 1 << ImmShift,
     Imm16    = 2 << ImmShift,
@@ -125,7 +129,7 @@ namespace X86II {
     // FP Instruction Classification...  Zero is non-fp instruction.
 
     // FPTypeMask - Mask for all of the FP types...
-    FPTypeShift = 12,
+    FPTypeShift = 13,
     FPTypeMask  = 7 << FPTypeShift,
 
     // NotFP - The default, set for instructions that do not use FP registers.
@@ -158,9 +162,9 @@ namespace X86II {
     SpecialFP  = 7 << FPTypeShift,
 
     // Bit 15 is unused.
-    OpcodeShift   = 16,
+    OpcodeShift   = 17,
     OpcodeMask    = 0xFF << OpcodeShift,
-    // Bits 24 -> 31 are unused
+    // Bits 25 -> 31 are unused
   };
 }
 

llvm/lib/Target/X86/X86InstrInfo.td

@@ -180,8 +180,8 @@ def leaaddr : ComplexPattern<i32, 4, "SelectLEAAddr",
 // Format specifies the encoding used by the instruction.  This is part of the
 // ad-hoc solution used to emit machine instruction encodings by our machine
 // code emitter.
-class Format<bits<5> val> {
-  bits<5> Value = val;
+class Format<bits<6> val> {
+  bits<6> Value = val;
 }
 
 def Pseudo     : Format<0>; def RawFrm     : Format<1>;
@@ -194,6 +194,7 @@ def MRM6r  : Format<22>; def MRM7r  : Format<23>;
 def MRM0m  : Format<24>; def MRM1m  : Format<25>; def MRM2m  : Format<26>;
 def MRM3m  : Format<27>; def MRM4m  : Format<28>; def MRM5m  : Format<29>;
 def MRM6m  : Format<30>; def MRM7m  : Format<31>;
+def MRMInitReg : Format<32>;
 
 //===----------------------------------------------------------------------===//
 // X86 Instruction Predicate Definitions.
@@ -238,7 +239,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
 
   bits<8> Opcode = opcod;
   Format Form = f;
-  bits<5> FormBits = Form.Value;
+  bits<6> FormBits = Form.Value;
   ImmType ImmT = i;
   bits<2> ImmTypeBits = ImmT.Value;
 
@@ -708,6 +709,18 @@ def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src),
                 "mov{l} {$src, $dst|$dst, $src}",
                 [(store R32:$src, addr:$dst)]>;
                 
+// Pseudo-instructions that map movr0 to xor.
+// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
+def MOV8r0   : I<0x30, MRMInitReg, (ops R8 :$dst),
+                 "xor{b} $dst, $dst",
+                 [(set R8:$dst, 0)]>;
+def MOV16r0  : I<0x31, MRMInitReg,  (ops R16:$dst), 
+                 "xor{w} $dst, $dst",
+                 [(set R16:$dst, 0)]>, OpSize;
+def MOV32r0  : I<0x31, MRMInitReg,  (ops R32:$dst), 
+                 "xor{l} $dst, $dst",
+                 [(set R32:$dst, 0)]>;
+
 //===----------------------------------------------------------------------===//
 //  Fixed-Register Multiplication and Division Instructions...
 //
@@ -2478,10 +2491,10 @@ def UCOMISSrm: I<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
 
 // Pseudo-instructions that map fld0 to xorps/xorpd for sse.
 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-def FLD0SS : I<0x57, MRMSrcReg, (ops FR32:$dst),
+def FLD0SS : I<0x57, MRMInitReg, (ops FR32:$dst),
                "xorps $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
              Requires<[HasSSE1]>, TB;
-def FLD0SD : I<0x57, MRMSrcReg, (ops FR64:$dst),
+def FLD0SD : I<0x57, MRMInitReg, (ops FR64:$dst),
                "xorpd $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
              Requires<[HasSSE2]>, TB, OpSize;