forked from OSchip/llvm-project
Convert the remaining instructions over, branches and calls. Fix a couple
minor bugs llvm-svn: 24762
This commit is contained in:
Chris Lattner
parent
6b669e2680
commit
9e2af046e4
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@ -1,11 +1,10 @@
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Meta TODO list:
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1. Convert all instructions to use autogeneration for asm strings.
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2. Convert asmprinter to use lib/CodeGen/AsmPrinter for global init printing
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1. Convert asmprinter to use lib/CodeGen/AsmPrinter for global init printing
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constant pool printing, etc.
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3. Create a new DAG -> DAG instruction selector, by adding patterns to the
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2. Create a new DAG -> DAG instruction selector, by adding patterns to the
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instructions.
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4. profit!
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3. profit!
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SparcV8 backend skeleton
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@ -70,7 +70,6 @@ namespace {
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void emitGlobalConstant(const Constant *CV);
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void printConstantPool(MachineConstantPool *MCP);
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void printOperand(const MachineInstr *MI, int opNum);
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void printMachineInstruction(const MachineInstr *MI);
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bool printInstruction(const MachineInstr *MI); // autogenerated.
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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@ -357,7 +356,8 @@ bool SparcV8AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
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II != E; ++II) {
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// Print the assembly for the instruction.
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printMachineInstruction(II);
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O << "\t";
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printInstruction(II);
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}
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}
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@ -421,42 +421,6 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
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if (CloseParen) O << ")";
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}
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/// printMachineInstruction -- Print out a single SparcV8 LLVM instruction
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/// MI in GAS syntax to the current output stream.
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///
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void SparcV8AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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O << "\t";
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if (printInstruction(MI)) return;
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unsigned Opcode = MI->getOpcode();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const TargetInstrDescriptor &Desc = TII.get(Opcode);
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O << Desc.Name << " ";
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// print non-immediate, non-register-def operands
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// then print immediate operands
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// then print register-def operands.
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std::vector<int> print_order;
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for (unsigned i = 0; i < MI->getNumOperands (); ++i)
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if (!(MI->getOperand (i).isImmediate ()
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|| (MI->getOperand (i).isRegister ()
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&& MI->getOperand (i).isDef ())))
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print_order.push_back (i);
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for (unsigned i = 0; i < MI->getNumOperands (); ++i)
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if (MI->getOperand (i).isImmediate ())
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print_order.push_back (i);
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for (unsigned i = 0; i < MI->getNumOperands (); ++i)
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if (MI->getOperand (i).isRegister () && MI->getOperand (i).isDef ())
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print_order.push_back (i);
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for (unsigned i = 0, e = print_order.size (); i != e; ++i) {
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printOperand (MI, print_order[i]);
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if (i != (print_order.size () - 1))
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O << ", ";
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}
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O << "\n";
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}
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bool SparcV8AsmPrinter::doInitialization(Module &M) {
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Mang = new Mangler(M);
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return false; // success
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@ -32,13 +32,15 @@ class F2_1<bits<3> op2Val, dag ops, string asmstr> : F2 {
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let Inst{29-25} = rd;
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}
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class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
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class F2_2<bits<4> condVal, bits<3> op2Val, dag ops, string asmstr> : F2 {
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bits<4> cond;
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bit annul = 0; // currently unused
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dag OperandList = ops;
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let AsmString = asmstr;
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let cond = condVal;
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let op2 = op2Val;
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let Name = name;
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let Inst{29} = annul;
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let Inst{28-25} = cond;
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@ -65,8 +65,8 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
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// FIXME: should keep track of the fact that it defs the integer condition codes
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let rd = 0 in
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def CMPri: F3_2<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"cmp $b, $c, $dst">;
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(ops IntRegs:$b, i32imm:$c),
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"cmp $b, $c">;
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// Section B.1 - Load Integer Instructions, p. 90
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def LDSB: F3_2<3, 0b001001,
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@ -373,51 +373,53 @@ def RESTOREri : F3_2<2, 0b111101,
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// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
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// conditional branch class:
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class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> {
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class BranchV8<bits<4> cc, dag ops, string asmstr>
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: F2_2<cc, 0b010, ops, asmstr> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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}
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let isBarrier = 1 in
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def BA : BranchV8<0b1000, "ba">;
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def BN : BranchV8<0b0000, "bn">;
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def BNE : BranchV8<0b1001, "bne">;
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def BE : BranchV8<0b0001, "be">;
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def BG : BranchV8<0b1010, "bg">;
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def BLE : BranchV8<0b0010, "ble">;
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def BGE : BranchV8<0b1011, "bge">;
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def BL : BranchV8<0b0011, "bl">;
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def BGU : BranchV8<0b1100, "bgu">;
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def BLEU : BranchV8<0b0100, "bleu">;
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def BCC : BranchV8<0b1101, "bcc">;
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def BCS : BranchV8<0b0101, "bcs">;
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def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">;
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def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">;
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def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">;
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def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">;
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def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">;
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def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">;
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def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">;
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def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">;
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def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">;
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def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">;
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def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">;
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def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">;
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// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
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// floating-point conditional branch class:
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class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> {
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class FPBranchV8<bits<4> cc, dag ops, string asmstr>
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: F2_2<cc, 0b110, ops, asmstr> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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}
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def FBA : FPBranchV8<0b1000, "fba">;
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def FBN : FPBranchV8<0b0000, "fbn">;
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def FBU : FPBranchV8<0b0111, "fbu">;
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def FBG : FPBranchV8<0b0110, "fbg">;
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def FBUG : FPBranchV8<0b0101, "fbug">;
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def FBL : FPBranchV8<0b0100, "fbl">;
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def FBUL : FPBranchV8<0b0011, "fbul">;
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def FBLG : FPBranchV8<0b0010, "fblg">;
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def FBNE : FPBranchV8<0b0001, "fbne">;
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def FBE : FPBranchV8<0b1001, "fbe">;
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def FBUE : FPBranchV8<0b1010, "fbue">;
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def FBGE : FPBranchV8<0b1011, "fbge">;
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def FBUGE: FPBranchV8<0b1100, "fbuge">;
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def FBLE : FPBranchV8<0b1101, "fble">;
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def FBULE: FPBranchV8<0b1110, "fbule">;
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def FBO : FPBranchV8<0b1111, "fbo">;
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def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">;
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def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">;
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def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">;
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def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">;
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def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">;
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def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">;
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def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">;
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def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">;
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def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">;
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def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">;
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def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">;
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def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">;
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def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">;
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def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">;
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def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">;
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def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">;
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@ -428,10 +430,11 @@ let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
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let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
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D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
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def CALL : InstV8 {
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let OperandList = (ops IntRegs:$dst);
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bits<30> disp;
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let op = 1;
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let Inst{29-0} = disp;
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let Name = "call";
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let AsmString = "call $dst";
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}
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// indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
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@ -524,13 +527,13 @@ def FDIVD : F3_3<2, 0b110100, 0b001001110,
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// is modelled with a forced noop after the instruction.
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def FCMPS : F3_3<2, 0b110101, 0b001010001,
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(ops FPRegs:$src1, FPRegs:$src2),
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"fcmps $src1, $src2\n nop">;
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"fcmps $src1, $src2\n\tnop">;
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def FCMPD : F3_3<2, 0b110101, 0b001010010,
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(ops DFPRegs:$src1, DFPRegs:$src2),
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"fcmpd $src1, $src2\n nop">;
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"fcmpd $src1, $src2\n\tnop">;
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def FCMPES : F3_3<2, 0b110101, 0b001010101,
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(ops FPRegs:$src1, FPRegs:$src2),
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"fcmpes $src1, $src2\n nop">;
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"fcmpes $src1, $src2\n\tnop">;
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def FCMPED : F3_3<2, 0b110101, 0b001010110,
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(ops DFPRegs:$src1, DFPRegs:$src2),
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"fcmped $src1, $src2\n nop">;
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"fcmped $src1, $src2\n\tnop">;
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