forked from OSchip/llvm-project
[AArch64] Improve orr+movk sequences for MOVi64imm.
The existing code has three different ways to try to lower a 64-bit immediate to the sequence ORR+MOVK. The result is messy: it misses some possible sequences, and the order of the checks means we sometimes emit two MOVKs when we only need one. Instead, just use a simple loop to try all possible two-instruction ORR+MOVK sequences. Differential Revision: https://reviews.llvm.org/D47176 llvm-svn: 333218
This commit is contained in:
Eli Friedman
parent
7d60b9052a
commit
9e177882aa
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@ -66,6 +66,11 @@ private:
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MachineBasicBlock::iterator &NextMBBI);
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bool expandMOVImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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unsigned BitSize);
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bool expandMOVImmSimple(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned BitSize,
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unsigned OneChunks,
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unsigned ZeroChunks);
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bool expandCMP_SWAP(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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unsigned LdarOp, unsigned StlrOp, unsigned CmpOp,
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@ -107,57 +112,6 @@ static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) {
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return (Imm >> (ChunkIdx * 16)) & 0xFFFF;
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}
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/// Helper function which replicates a 16-bit chunk within a 64-bit
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/// value. Indices correspond to element numbers in a v4i16.
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static uint64_t replicateChunk(uint64_t Imm, unsigned FromIdx, unsigned ToIdx) {
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assert((FromIdx < 4) && (ToIdx < 4) && "Out of range chunk index specified!");
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const unsigned ShiftAmt = ToIdx * 16;
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// Replicate the source chunk to the destination position.
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const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt;
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// Clear the destination chunk.
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Imm &= ~(0xFFFFLL << ShiftAmt);
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// Insert the replicated chunk.
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return Imm | Chunk;
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}
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/// Helper function which tries to materialize a 64-bit value with an
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/// ORR + MOVK instruction sequence.
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static bool tryOrrMovk(uint64_t UImm, uint64_t OrrImm, MachineInstr &MI,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const AArch64InstrInfo *TII, unsigned ChunkIdx) {
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assert(ChunkIdx < 4 && "Out of range chunk index specified!");
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const unsigned ShiftAmt = ChunkIdx * 16;
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uint64_t Encoding;
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if (AArch64_AM::processLogicalImmediate(OrrImm, 64, Encoding)) {
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// Create the ORR-immediate instruction.
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
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.add(MI.getOperand(0))
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.addReg(AArch64::XZR)
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.addImm(Encoding);
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// Create the MOVK instruction.
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const unsigned Imm16 = getChunk(UImm, ChunkIdx);
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const unsigned DstReg = MI.getOperand(0).getReg();
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const bool DstIsDead = MI.getOperand(0).isDead();
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MachineInstrBuilder MIB1 =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
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.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstReg)
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.addImm(Imm16)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
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transferImpOps(MI, MIB, MIB1);
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MI.eraseFromParent();
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return true;
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}
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return false;
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}
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/// Check whether the given 16-bit chunk replicated to full 64-bit width
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/// can be materialized with an ORR instruction.
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static bool canUseOrr(uint64_t Chunk, uint64_t &Encoding) {
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@ -440,7 +394,22 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
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return true;
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}
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// Try a MOVI instruction (aka ORR-immediate with the zero register).
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// Scan the immediate and count the number of 16-bit chunks which are either
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// all ones or all zeros.
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unsigned OneChunks = 0;
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unsigned ZeroChunks = 0;
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for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {
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const unsigned Chunk = (Imm >> Shift) & Mask;
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if (Chunk == Mask)
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OneChunks++;
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else if (Chunk == 0)
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ZeroChunks++;
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}
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// FIXME: Prefer MOVZ/MOVN over ORR because of the rules for the "mov"
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// alias.
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// Try a single ORR.
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uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
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uint64_t Encoding;
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if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
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@ -455,74 +424,69 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
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return true;
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}
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// Scan the immediate and count the number of 16-bit chunks which are either
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// all ones or all zeros.
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unsigned OneChunks = 0;
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unsigned ZeroChunks = 0;
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// Two instruction sequences.
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//
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// Prefer MOVZ/MOVN followed by MOVK; it's more readable, and possibly the
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// fastest sequence with fast literal generation.
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if (OneChunks >= (BitSize / 16) - 2 || ZeroChunks >= (BitSize / 16) - 2)
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return expandMOVImmSimple(MBB, MBBI, BitSize, OneChunks, ZeroChunks);
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assert(BitSize == 64 && "All 32-bit immediates can be expanded with a"
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"MOVZ/MOVK pair");
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// Try other two-instruction sequences.
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// 64-bit ORR followed by MOVK.
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// We try to construct the ORR immediate in three different ways: either we
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// zero out the chunk which will be replaced, we fill the chunk which will
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// be replaced with ones, or we take the bit pattern from the other half of
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// the 64-bit immediate. This is comprehensive because of the way ORR
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// immediates are constructed.
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for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {
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const unsigned Chunk = (Imm >> Shift) & Mask;
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if (Chunk == Mask)
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OneChunks++;
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else if (Chunk == 0)
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ZeroChunks++;
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}
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uint64_t ShiftedMask = (0xFFFFULL << Shift);
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uint64_t ZeroChunk = UImm & ~ShiftedMask;
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uint64_t OneChunk = UImm | ShiftedMask;
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uint64_t RotatedImm = (UImm << 32) | (UImm >> 32);
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uint64_t ReplicateChunk = ZeroChunk | (RotatedImm & ShiftedMask);
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if (AArch64_AM::processLogicalImmediate(ZeroChunk, BitSize, Encoding) ||
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AArch64_AM::processLogicalImmediate(OneChunk, BitSize, Encoding) ||
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AArch64_AM::processLogicalImmediate(ReplicateChunk,
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BitSize, Encoding)) {
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// Create the ORR-immediate instruction.
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
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.add(MI.getOperand(0))
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.addReg(AArch64::XZR)
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.addImm(Encoding);
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// Since we can't materialize the constant with a single ORR instruction,
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// let's see whether we can materialize 3/4 of the constant with an ORR
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// instruction and use an additional MOVK instruction to materialize the
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// remaining 1/4.
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//
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// We are looking for constants with a pattern like: |A|X|B|X| or |X|A|X|B|.
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//
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// E.g. assuming |A|X|A|X| is a pattern which can be materialized with ORR,
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// we would create the following instruction sequence:
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//
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// ORR x0, xzr, |A|X|A|X|
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// MOVK x0, |B|, LSL #16
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//
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// Only look at 64-bit constants which can't be materialized with a single
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// instruction e.g. which have less than either three all zero or all one
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// chunks.
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//
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// Ignore 32-bit constants here, they always can be materialized with a
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// MOVZ/MOVN + MOVK pair. Since the 32-bit constant can't be materialized
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// with a single ORR, the best sequence we can achieve is a ORR + MOVK pair.
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// Thus we fall back to the default code below which in the best case creates
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// a single MOVZ/MOVN instruction (in case one chunk is all zero or all one).
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//
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if (BitSize == 64 && OneChunks < 3 && ZeroChunks < 3) {
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// If we interpret the 64-bit constant as a v4i16, are elements 0 and 2
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// identical?
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if (getChunk(UImm, 0) == getChunk(UImm, 2)) {
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// See if we can come up with a constant which can be materialized with
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// ORR-immediate by replicating element 3 into element 1.
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uint64_t OrrImm = replicateChunk(UImm, 3, 1);
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if (tryOrrMovk(UImm, OrrImm, MI, MBB, MBBI, TII, 1))
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return true;
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// Create the MOVK instruction.
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const unsigned Imm16 = getChunk(UImm, Shift / 16);
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const unsigned DstReg = MI.getOperand(0).getReg();
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const bool DstIsDead = MI.getOperand(0).isDead();
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MachineInstrBuilder MIB1 =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
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.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstReg)
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.addImm(Imm16)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift));
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// See if we can come up with a constant which can be materialized with
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// ORR-immediate by replicating element 1 into element 3.
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OrrImm = replicateChunk(UImm, 1, 3);
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if (tryOrrMovk(UImm, OrrImm, MI, MBB, MBBI, TII, 3))
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return true;
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// If we interpret the 64-bit constant as a v4i16, are elements 1 and 3
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// identical?
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} else if (getChunk(UImm, 1) == getChunk(UImm, 3)) {
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// See if we can come up with a constant which can be materialized with
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// ORR-immediate by replicating element 2 into element 0.
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uint64_t OrrImm = replicateChunk(UImm, 2, 0);
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if (tryOrrMovk(UImm, OrrImm, MI, MBB, MBBI, TII, 0))
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return true;
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// See if we can come up with a constant which can be materialized with
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// ORR-immediate by replicating element 1 into element 3.
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OrrImm = replicateChunk(UImm, 0, 2);
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if (tryOrrMovk(UImm, OrrImm, MI, MBB, MBBI, TII, 2))
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return true;
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transferImpOps(MI, MIB, MIB1);
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MI.eraseFromParent();
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return true;
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}
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}
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// FIXME: Add more two-instruction sequences.
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// Three instruction sequences.
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//
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// Prefer MOVZ/MOVN followed by two MOVK; it's more readable, and possibly
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// the fastest sequence with fast literal generation. (If neither MOVK is
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// part of a fast literal generation pair, it could be slower than the
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// four-instruction sequence, but we won't worry about that for now.)
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if (OneChunks || ZeroChunks)
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return expandMOVImmSimple(MBB, MBBI, BitSize, OneChunks, ZeroChunks);
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// Check for identical 16-bit chunks within the constant and if so materialize
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// them with a single ORR instruction. The remaining one or two 16-bit chunks
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// will be materialized with MOVK instructions.
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@ -537,6 +501,23 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
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if (BitSize == 64 && trySequenceOfOnes(UImm, MI, MBB, MBBI, TII))
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return true;
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// We found no possible two or three instruction sequence; use the general
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// four-instruction sequence.
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return expandMOVImmSimple(MBB, MBBI, BitSize, OneChunks, ZeroChunks);
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}
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/// \brief Expand a MOVi32imm or MOVi64imm pseudo instruction to a
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/// MOVZ or MOVN of width BitSize followed by up to 3 MOVK instructions.
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bool AArch64ExpandPseudo::expandMOVImmSimple(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned BitSize,
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unsigned OneChunks,
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unsigned ZeroChunks) {
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MachineInstr &MI = *MBBI;
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unsigned DstReg = MI.getOperand(0).getReg();
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uint64_t Imm = MI.getOperand(1).getImm();
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const unsigned Mask = 0xFFFF;
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// Use a MOVZ or MOVN instruction to set the high bits, followed by one or
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// more MOVK instructions to insert additional 16-bit portions into the
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// lower bits.
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@ -134,18 +134,6 @@ define i64 @mvn_lsl_pattern() nounwind {
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ret i64 -279156097024
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}
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; FIXME: prefer "mov w0, #-63; movk x0, #31, lsl #32"
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; or "mov x0, #137438887936; movk x0, #65473"
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define i64 @mvn32_pattern() nounwind {
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; CHECK-LABEL: mvn32_pattern:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #65473
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; CHECK-NEXT: movk x0, #65535, lsl #16
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; CHECK-NEXT: movk x0, #31, lsl #32
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; CHECK-NEXT: ret
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ret i64 137438953409
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}
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; FIXME: prefer "mov w0, #-63; movk x0, #17, lsl #32"
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define i64 @mvn32_pattern_2() nounwind {
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; CHECK-LABEL: mvn32_pattern_2:
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@ -281,9 +269,9 @@ define i64 @orr_movk10() nounwind {
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define i64 @orr_movk11() nounwind {
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; CHECK-LABEL: orr_movk11:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-4503599627370241
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; CHECK-NEXT: mov x0, #-65281
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; CHECK-NEXT: movk x0, #57005, lsl #16
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; CHECK-NEXT: movk x0, #65535, lsl #32
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; CHECK-NEXT: movk x0, #65520, lsl #48
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; CHECK-NEXT: ret
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ret i64 -4222125209747201
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}
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@ -318,24 +306,20 @@ entry:
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ret i64 -281474976710654
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}
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; FIXME: prefer "mov x0, #-549755813888; movk x0, 2048, lsl #16"
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define i64 @orr_movk14() nounwind {
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; CHECK-LABEL: orr_movk14:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #134217728
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; CHECK-NEXT: movk x0, #65408, lsl #32
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; CHECK-NEXT: movk x0, #65535, lsl #48
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; CHECK-NEXT: mov x0, #-549755813888
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; CHECK-NEXT: movk x0, #2048, lsl #16
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; CHECK-NEXT: ret
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ret i64 -549621596160
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}
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; FIXME: prefer "mov x0, #549755813887; movk x0, #63487, lsl #16"
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define i64 @orr_movk15() nounwind {
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; CHECK-LABEL: orr_movk15:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #65535
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; CHECK-NEXT: mov x0, #549755813887
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; CHECK-NEXT: movk x0, #63487, lsl #16
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; CHECK-NEXT: movk x0, #127, lsl #32
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; CHECK-NEXT: ret
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ret i64 549621596159
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}
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@ -351,24 +335,121 @@ define i64 @orr_movk16() nounwind {
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ret i64 36028661727494142
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}
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; FIXME: prefer "mov x0, #-1099511627776; movk x0, #65280, lsl #16"
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define i64 @orr_movk17() nounwind {
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; CHECK-LABEL: orr_movk17:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-71777214294589696
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; CHECK-NEXT: movk x0, #0
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; CHECK-NEXT: movk x0, #65535, lsl #48
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; CHECK-NEXT: mov x0, #-1099511627776
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; CHECK-NEXT: movk x0, #65280, lsl #16
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; CHECK-NEXT: ret
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ret i64 -1095233437696
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}
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; FIXME: prefer "mov x0, #72340172838076673; and x0, x0, #2199023255296"
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define i64 @orr_movk18() nounwind {
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; CHECK-LABEL: orr_movk18:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #72340172838076673
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; CHECK-NEXT: movk x0, #256
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; CHECK-NEXT: movk x0, #0, lsl #48
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; CHECK-NEXT: mov x0, #137438887936
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; CHECK-NEXT: movk x0, #65473
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; CHECK-NEXT: ret
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ret i64 137438953409
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}
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; FIXME: prefer "mov x0, #72340172838076673; and x0, x0, #2199023255296"
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define i64 @orr_and() nounwind {
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; CHECK-LABEL: orr_and:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #256
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; CHECK-NEXT: movk x0, #257, lsl #16
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; CHECK-NEXT: movk x0, #257, lsl #32
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; CHECK-NEXT: ret
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ret i64 1103823438080
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}
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; FIXME: prefer "mov w0, #-1431655766; movk x0, #9, lsl #32"
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define i64 @movn_movk() nounwind {
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; CHECK-LABEL: movn_movk:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #43690
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; CHECK-NEXT: movk x0, #43690, lsl #16
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; CHECK-NEXT: movk x0, #9, lsl #32
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; CHECK-NEXT: ret
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ret i64 41518017194
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}
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; FIXME: prefer "mov w0, #-13690; orr x0, x0, #0x1111111111111111"
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define i64 @movn_orr() nounwind {
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; CHECK-LABEL: movn_orr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-51847
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; CHECK-NEXT: movk x0, #4369, lsl #32
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; CHECK-NEXT: movk x0, #4369, lsl #48
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; CHECK-NEXT: ret
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ret i64 1229782942255887737
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}
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; FIXME: prefer "mov w0, #-305397761; eor x0, x0, #0x3333333333333333"
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define i64 @movn_eor() nounwind {
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; CHECK-LABEL: movn_eor:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #3689348814741910323
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; CHECK-NEXT: movk x0, #52428
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; CHECK-NEXT: movk x0, #8455, lsl #16
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; CHECK-NEXT: ret
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ret i64 3689348814437076172
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}
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; FIXME: prefer "mov x0, #536866816; orr x0, x0, #0x3fff800000000000"
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||||
define i64 @orr_orr_64() nounwind {
|
||||
; CHECK-LABEL: orr_orr_64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: mov x0, #4611545280939032576
|
||||
; CHECK-NEXT: movk x0, #61440
|
||||
; CHECK-NEXT: movk x0, #8191, lsl #16
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 4611545281475899392
|
||||
}
|
||||
|
||||
; FIXME: prefer "mov x0, #558551907040256; orr x0, x0, #0x1000100010001000"
|
||||
define i64 @orr_orr_32() nounwind {
|
||||
; CHECK-LABEL: orr_orr_32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: mov x0, #-287953294993589248
|
||||
; CHECK-NEXT: movk x0, #7169, lsl #16
|
||||
; CHECK-NEXT: movk x0, #7169, lsl #48
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 2018171185438784512
|
||||
}
|
||||
|
||||
; FIXME: prefer "mov x0, #281479271743489; orr x0, x0, #0x1000100010001000"
|
||||
define i64 @orr_orr_16() nounwind {
|
||||
; CHECK-LABEL: orr_orr_16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: mov x0, #4097
|
||||
; CHECK-NEXT: movk x0, #4097, lsl #16
|
||||
; CHECK-NEXT: movk x0, #4097, lsl #32
|
||||
; CHECK-NEXT: movk x0, #4097, lsl #48
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 1153220576333074433
|
||||
}
|
||||
|
||||
; FIXME: prefer "mov x0, #144680345676153346; orr x0, x0, #0x1818181818181818"
|
||||
define i64 @orr_orr_8() nounwind {
|
||||
; CHECK-LABEL: orr_orr_8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: mov x0, #6682
|
||||
; CHECK-NEXT: movk x0, #6682, lsl #16
|
||||
; CHECK-NEXT: movk x0, #6682, lsl #32
|
||||
; CHECK-NEXT: movk x0, #6682, lsl #48
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 1880844493789993498
|
||||
}
|
||||
|
||||
; FIXME: prefer "mov x0, #-6148914691236517206; orr x0, x0, #0x0FFFFF0000000000"
|
||||
define i64 @orr_64_orr_8() nounwind {
|
||||
; CHECK-LABEL: orr_64_orr_8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: mov x0, #-6148914691236517206
|
||||
; CHECK-NEXT: movk x0, #65450, lsl #32
|
||||
; CHECK-NEXT: movk x0, #45055, lsl #48
|
||||
; CHECK-NEXT: ret
|
||||
ret i64 -5764607889538110806
|
||||
}
|
||||
|
|
|
|||
|
|
@ -32,8 +32,8 @@ define void @test_simple(i32 %n, ...) {
|
|||
; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #128
|
||||
; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16]
|
||||
|
||||
; CHECK: mov [[GRVR:x[0-9]+]], #-545460846720
|
||||
; CHECK: movk [[GRVR]], #65480
|
||||
; CHECK: mov [[GRVR:x[0-9]+]], #-56
|
||||
; CHECK: movk [[GRVR]], #65408, lsl #32
|
||||
; CHECK: str [[GRVR]], [x[[VA_LIST]], #24]
|
||||
|
||||
%addr = bitcast %va_list* @var to i8*
|
||||
|
|
|
|||
Loading…
Reference in New Issue