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[ARM] Add ARMv8.6 Fine Grain Traps system registers 

Summary:
This patch upstreams support for the ARMv8.6A Fine Grain Traps (FGT)
extension, which adds 5 new system registers.

See ARMv8.6-FGT in the Arm Architecture Reference Manual Armv8 for more
information.

Reviewers: t.p.northover, rengolin, SjoerdMeijer, ab, momchil.velikov

Reviewed By: SjoerdMeijer

Subscribers: LukeGeeson, ostannard, kristof.beyls, hiraditya, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76991
This commit is contained in:
Oliver Stannard 2020-04-05 13:58:00 +01:00 committed by Ties Stuij
parent 4036a0af24
commit 9e1455dc23
5 changed files with 89 additions and 1 deletions
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7
llvm/lib/Target/AArch64/AArch64.td
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@ -373,6 +373,10 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16",
"true", "Enable BFloat16 Extension" >;
def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
"true", "Enable fine grained virtualization traps extension">;
//===----------------------------------------------------------------------===//
// Architectures.
//
@ -403,7 +407,8 @@ def HasV8_5aOps : SubtargetFeature<
def HasV8_6aOps : SubtargetFeature<
"v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
[HasV8_5aOps, FeatureAMVS, FeatureBF16]>;
[HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps]>;
//===----------------------------------------------------------------------===//
// Register File Description

2
llvm/lib/Target/AArch64/AArch64Subtarget.h
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@ -148,6 +148,7 @@ protected:
// Armv8.6-A Extensions
bool HasBF16 = false;
bool HasAMVS = false;
bool HasFineGrainedTraps = false;
// Arm SVE2 extensions
bool HasSVE2AES = false;
@ -415,6 +416,7 @@ public:
// Armv8.6-A Extensions
bool hasBF16() const { return HasBF16; }
bool hasFineGrainedTraps() const { return HasFineGrainedTraps; }
bool isLittleEndian() const { return IsLittle; }

10
llvm/lib/Target/AArch64/AArch64SystemOperands.td
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@ -1502,6 +1502,16 @@ foreach n = 0-15 in {
}
}
// v8.6a Fine Grained Virtualization Traps
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureFineGrainedTraps} }] in {
def : RWSysReg<"HFGRTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b100>;
def : RWSysReg<"HFGWTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b101>;
def : RWSysReg<"HFGITR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b110>;
def : RWSysReg<"HDFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b100>;
def : RWSysReg<"HDFGWTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b101>;
}
// Cyclone specific system registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::ProcAppleA7} }] in

35
llvm/test/MC/AArch64/armv8.6a-fgt.s Normal file
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@ -0,0 +1,35 @@
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+fgt < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a < %s | FileCheck %s
// RUN: not llvm-mc -triple aarch64 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=NOFGT
msr HFGRTR_EL2, x0
msr HFGWTR_EL2, x5
msr HFGITR_EL2, x10
msr HDFGRTR_EL2, x15
msr HDFGWTR_EL2, x20
// CHECK: msr HFGRTR_EL2, x0 // encoding: [0x80,0x11,0x1c,0xd5]
// CHECK: msr HFGWTR_EL2, x5 // encoding: [0xa5,0x11,0x1c,0xd5]
// CHECK: msr HFGITR_EL2, x10 // encoding: [0xca,0x11,0x1c,0xd5]
// CHECK: msr HDFGRTR_EL2, x15 // encoding: [0x8f,0x31,0x1c,0xd5]
// CHECK: msr HDFGWTR_EL2, x20 // encoding: [0xb4,0x31,0x1c,0xd5]
// NOFGT: error: expected writable system register or pstate
// NOFGT: error: expected writable system register or pstate
// NOFGT: error: expected writable system register or pstate
// NOFGT: error: expected writable system register or pstate
// NOFGT: error: expected writable system register or pstate
mrs x30, HFGRTR_EL2
mrs x25, HFGWTR_EL2
mrs x20, HFGITR_EL2
mrs x15, HDFGRTR_EL2
mrs x10, HDFGWTR_EL2
// CHECK: mrs x30, HFGRTR_EL2 // encoding: [0x9e,0x11,0x3c,0xd5]
// CHECK: mrs x25, HFGWTR_EL2 // encoding: [0xb9,0x11,0x3c,0xd5]
// CHECK: mrs x20, HFGITR_EL2 // encoding: [0xd4,0x11,0x3c,0xd5]
// CHECK: mrs x15, HDFGRTR_EL2 // encoding: [0x8f,0x31,0x3c,0xd5]
// CHECK: mrs x10, HDFGWTR_EL2 // encoding: [0xaa,0x31,0x3c,0xd5]
// NOFGT: error: expected readable system register
// NOFGT: error: expected readable system register
// NOFGT: error: expected readable system register
// NOFGT: error: expected readable system register
// NOFGT: error: expected readable system register

36
llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt Normal file
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@ -0,0 +1,36 @@
# RUN: llvm-mc -triple=aarch64 -mattr=+fgt -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOFGT
[0x80,0x11,0x1c,0xd5]
[0xa0,0x11,0x1c,0xd5]
[0xc0,0x11,0x1c,0xd5]
[0x80,0x31,0x1c,0xd5]
[0xa0,0x31,0x1c,0xd5]
# CHECK: msr HFGRTR_EL2, x0
# CHECK: msr HFGWTR_EL2, x0
# CHECK: msr HFGITR_EL2, x0
# CHECK: msr HDFGRTR_EL2, x0
# CHECK: msr HDFGWTR_EL2, x0
# NOFGT: msr S3_4_C1_C1_4, x0
# NOFGT: msr S3_4_C1_C1_5, x0
# NOFGT: msr S3_4_C1_C1_6, x0
# NOFGT: msr S3_4_C3_C1_4, x0
# NOFGT: msr S3_4_C3_C1_5, x0
[0x80,0x11,0x3c,0xd5]
[0xa0,0x11,0x3c,0xd5]
[0xc0,0x11,0x3c,0xd5]
[0x80,0x31,0x3c,0xd5]
[0xa0,0x31,0x3c,0xd5]
# CHECK: mrs x0, HFGRTR_EL2
# CHECK: mrs x0, HFGWTR_EL2
# CHECK: mrs x0, HFGITR_EL2
# CHECK: mrs x0, HDFGRTR_EL2
# CHECK: mrs x0, HDFGWTR_EL2
# NOFGT: mrs x0, S3_4_C1_C1_4
# NOFGT: mrs x0, S3_4_C1_C1_5
# NOFGT: mrs x0, S3_4_C1_C1_6
# NOFGT: mrs x0, S3_4_C3_C1_4
# NOFGT: mrs x0, S3_4_C3_C1_5