forked from OSchip/llvm-project
[X86] Remove mayLoad flag from BNDMK/BNDCL/BNDCN/BNDCU.
The instruction documentation specifically says that these instruction don't access memory. llvm-svn: 331105
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@ -17,7 +17,6 @@
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let SchedRW = [WriteSystem] in {
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multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
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let mayLoad = 1 in {
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def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
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OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
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Requires<[HasMPX, Not64BitMode]>;
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@ -25,19 +24,17 @@ let mayLoad = 1 in {
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OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
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Requires<[HasMPX, In64BitMode]>;
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}
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}
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defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS;
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multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
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let mayLoad = 1 in {
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def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
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OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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Requires<[HasMPX, Not64BitMode]>;
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def 64rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
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OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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Requires<[HasMPX, In64BitMode]>;
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}
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def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
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OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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Requires<[HasMPX, Not64BitMode]>;
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