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Tidyup for loops - don't repeat upper limit evaluation if you don't have to. NFCI. 

llvm-svn: 262137
This commit is contained in:
Simon Pilgrim 2016-02-27 13:26:58 +00:00
parent b1be8f6928
commit 9e10b1655c
1 changed files with 5 additions and 5 deletions
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10
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -2210,7 +2210,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
MVT::i16)); MVT::i16));
// Copy the result values into the output registers. // Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) { for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
CCValAssign &VA = RVLocs[i]; CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!"); assert(VA.isRegLoc() && "Can only return in registers!");
SDValue ValToCopy = OutVals[i]; SDValue ValToCopy = OutVals[i];
@ -6075,7 +6075,7 @@ X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
DAG.getIntPtrConstant(0, dl)); DAG.getIntPtrConstant(0, dl));
} }
for (unsigned i = 0; i < NonConstIdx.size(); ++i) { for (unsigned i = 0, e = NonConstIdx.size(); i != e; ++i) {
unsigned InsertIdx = NonConstIdx[i]; unsigned InsertIdx = NonConstIdx[i];
DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
Op.getOperand(InsertIdx), Op.getOperand(InsertIdx),
@ -26367,6 +26367,7 @@ static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
return SDValue(); return SDValue();
unsigned SrcSize = SrcType.getScalarSizeInBits(); unsigned SrcSize = SrcType.getScalarSizeInBits();
unsigned NumElems = SrcType.getVectorNumElements();
APInt SplatValue, SplatUndef; APInt SplatValue, SplatUndef;
unsigned SplatBitSize; unsigned SplatBitSize;
@ -26390,7 +26391,7 @@ static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
// the source and dest type. // the source and dest type.
unsigned ZextRatio = ResSize / SrcSize; unsigned ZextRatio = ResSize / SrcSize;
bool IsZext = true; bool IsZext = true;
for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) { for (unsigned i = 0; i != NumElems; ++i) {
if (i % ZextRatio) { if (i % ZextRatio) {
if (Shuffle->getMaskElt(i) > 0) { if (Shuffle->getMaskElt(i) > 0) {
// Expected undef // Expected undef
@ -26413,8 +26414,7 @@ static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
// a shuffle of the form <0, k, k, k, 1, k, k, k> with zero // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
// (instead of undef) where the k elements come from the zero vector. // (instead of undef) where the k elements come from the zero vector.
SmallVector<int, 8> Mask; SmallVector<int, 8> Mask;
unsigned NumElems = SrcType.getVectorNumElements(); for (unsigned i = 0; i != NumElems; ++i)
for (unsigned i = 0; i < NumElems; ++i)
if (i % ZextRatio) if (i % ZextRatio)
Mask.push_back(NumElems); Mask.push_back(NumElems);
else else