forked from OSchip/llvm-project
Tidyup for loops - don't repeat upper limit evaluation if you don't have to. NFCI.
llvm-svn: 262137
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@ -2210,7 +2210,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
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MVT::i16));
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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SDValue ValToCopy = OutVals[i];
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@ -6075,7 +6075,7 @@ X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
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DAG.getIntPtrConstant(0, dl));
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}
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for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
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for (unsigned i = 0, e = NonConstIdx.size(); i != e; ++i) {
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unsigned InsertIdx = NonConstIdx[i];
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DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
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Op.getOperand(InsertIdx),
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@ -26367,6 +26367,7 @@ static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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unsigned SrcSize = SrcType.getScalarSizeInBits();
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unsigned NumElems = SrcType.getVectorNumElements();
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APInt SplatValue, SplatUndef;
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unsigned SplatBitSize;
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@ -26390,7 +26391,7 @@ static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
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// the source and dest type.
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unsigned ZextRatio = ResSize / SrcSize;
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bool IsZext = true;
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for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
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for (unsigned i = 0; i != NumElems; ++i) {
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if (i % ZextRatio) {
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if (Shuffle->getMaskElt(i) > 0) {
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// Expected undef
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@ -26413,8 +26414,7 @@ static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
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// a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
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// (instead of undef) where the k elements come from the zero vector.
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SmallVector<int, 8> Mask;
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unsigned NumElems = SrcType.getVectorNumElements();
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for (unsigned i = 0; i < NumElems; ++i)
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for (unsigned i = 0; i != NumElems; ++i)
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if (i % ZextRatio)
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Mask.push_back(NumElems);
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else
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