forked from OSchip/llvm-project
GlobalISel: Handle odd breakdowns for bit ops
llvm-svn: 358105
This commit is contained in:
Matt Arsenault
parent
8b36ac818c
commit
9e0eeba569
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@ -210,6 +210,7 @@ private:
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LegalizeResult narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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@ -654,46 +654,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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// ...
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// AN = BinOp<Ty/N> BN, CN
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// A = G_MERGE_VALUES A1, ..., AN
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// FIXME: add support for when SizeOp0 isn't an exact multiple of
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// NarrowSize.
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if (SizeOp0 % NarrowSize != 0)
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return UnableToLegalize;
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int NumParts = SizeOp0 / NarrowSize;
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// List the registers where the destination will be scattered.
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SmallVector<unsigned, 2> DstRegs;
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// List the registers where the first argument will be split.
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SmallVector<unsigned, 2> SrcsReg1;
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// List the registers where the second argument will be split.
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SmallVector<unsigned, 2> SrcsReg2;
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// Create all the temporary registers.
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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unsigned SrcReg1 = MRI.createGenericVirtualRegister(NarrowTy);
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unsigned SrcReg2 = MRI.createGenericVirtualRegister(NarrowTy);
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DstRegs.push_back(DstReg);
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SrcsReg1.push_back(SrcReg1);
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SrcsReg2.push_back(SrcReg2);
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}
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// Explode the big arguments into smaller chunks.
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MIRBuilder.buildUnmerge(SrcsReg1, MI.getOperand(1).getReg());
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MIRBuilder.buildUnmerge(SrcsReg2, MI.getOperand(2).getReg());
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// Do the operation on each small part.
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for (int i = 0; i < NumParts; ++i)
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MIRBuilder.buildInstr(MI.getOpcode(), {DstRegs[i]},
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{SrcsReg1[i], SrcsReg2[i]});
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// Gather the destination registers into the final destination.
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unsigned DstReg = MI.getOperand(0).getReg();
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if(MRI.getType(DstReg).isVector())
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MIRBuilder.buildBuildVector(DstReg, DstRegs);
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else
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MIRBuilder.buildMerge(DstReg, DstRegs);
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MI.eraseFromParent();
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return Legalized;
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return narrowScalarBasic(MI, TypeIdx, NarrowTy);
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}
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case TargetOpcode::G_SHL:
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case TargetOpcode::G_LSHR:
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@ -2788,6 +2749,47 @@ LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
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return Legalized;
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy) {
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unsigned DstReg = MI.getOperand(0).getReg();
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LLT DstTy = MRI.getType(DstReg);
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assert(MI.getNumOperands() == 3 && TypeIdx == 0);
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SmallVector<unsigned, 4> DstRegs, DstLeftoverRegs;
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SmallVector<unsigned, 4> Src0Regs, Src0LeftoverRegs;
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SmallVector<unsigned, 4> Src1Regs, Src1LeftoverRegs;
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LLT LeftoverTy;
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if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
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Src0Regs, Src0LeftoverRegs))
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return UnableToLegalize;
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LLT Unused;
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if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
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Src1Regs, Src1LeftoverRegs))
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llvm_unreachable("inconsistent extractParts result");
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for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
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auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
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{Src0Regs[I], Src1Regs[I]});
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DstRegs.push_back(Inst->getOperand(0).getReg());
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}
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for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
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auto Inst = MIRBuilder.buildInstr(
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MI.getOpcode(),
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{LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
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DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
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}
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insertParts(DstReg, DstTy, NarrowTy, DstRegs,
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LeftoverTy, DstLeftoverRegs);
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MI.eraseFromParent();
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return Legalized;
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy) {
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@ -55,6 +55,52 @@ body: |
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: test_and_s96
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
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; CHECK-LABEL: name: test_and_s96
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; CHECK: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
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; CHECK: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
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; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s96), 0
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; CHECK: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s96), 64
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; CHECK: [[EXTRACT2:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s96), 0
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; CHECK: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s96), 64
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; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[EXTRACT]], [[EXTRACT2]]
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[EXTRACT1]], [[EXTRACT3]]
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; CHECK: [[DEF:%[0-9]+]]:_(s96) = G_IMPLICIT_DEF
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; CHECK: [[INSERT:%[0-9]+]]:_(s96) = G_INSERT [[DEF]], [[AND]](s64), 0
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; CHECK: [[INSERT1:%[0-9]+]]:_(s96) = G_INSERT [[INSERT]], [[AND1]](s32), 64
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; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[INSERT1]](s96)
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%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
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%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
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%2:_(s96) = G_AND %0, %1
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$vgpr0_vgpr1_vgpr2 = COPY %2
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...
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---
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name: test_and_128
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK-LABEL: name: test_and_128
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; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
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; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128)
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; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[UV2]]
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; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[UV3]]
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; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[AND]](s64), [[AND1]](s64)
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; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
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%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(s128) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
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%2:_(s128) = G_AND %0, %1
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
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...
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---
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name: test_and_s7
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body: |
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@ -55,6 +55,52 @@ body: |
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: test_or_s96
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
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; CHECK-LABEL: name: test_or_s96
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; CHECK: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
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; CHECK: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
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; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s96), 0
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; CHECK: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s96), 64
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; CHECK: [[EXTRACT2:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s96), 0
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; CHECK: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s96), 64
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; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[EXTRACT]], [[EXTRACT2]]
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; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[EXTRACT1]], [[EXTRACT3]]
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; CHECK: [[DEF:%[0-9]+]]:_(s96) = G_IMPLICIT_DEF
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; CHECK: [[INSERT:%[0-9]+]]:_(s96) = G_INSERT [[DEF]], [[OR]](s64), 0
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; CHECK: [[INSERT1:%[0-9]+]]:_(s96) = G_INSERT [[INSERT]], [[OR1]](s32), 64
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; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[INSERT1]](s96)
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%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
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%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
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%2:_(s96) = G_OR %0, %1
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$vgpr0_vgpr1_vgpr2 = COPY %2
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...
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---
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name: test_or_128
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK-LABEL: name: test_or_128
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; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
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; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128)
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; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[UV]], [[UV2]]
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; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[UV1]], [[UV3]]
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; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[OR]](s64), [[OR1]](s64)
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; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
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%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(s128) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
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%2:_(s128) = G_OR %0, %1
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
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...
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---
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name: test_or_s7
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body: |
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@ -55,6 +55,52 @@ body: |
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: test_xor_s96
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5
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; CHECK-LABEL: name: test_xor_s96
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; CHECK: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
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; CHECK: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr3_vgpr4_vgpr5
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; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s96), 0
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; CHECK: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s96), 64
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; CHECK: [[EXTRACT2:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s96), 0
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; CHECK: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s96), 64
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; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[EXTRACT]], [[EXTRACT2]]
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; CHECK: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[EXTRACT1]], [[EXTRACT3]]
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; CHECK: [[DEF:%[0-9]+]]:_(s96) = G_IMPLICIT_DEF
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; CHECK: [[INSERT:%[0-9]+]]:_(s96) = G_INSERT [[DEF]], [[XOR]](s64), 0
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; CHECK: [[INSERT1:%[0-9]+]]:_(s96) = G_INSERT [[INSERT]], [[XOR1]](s32), 64
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; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[INSERT1]](s96)
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%0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
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%1:_(s96) = COPY $vgpr3_vgpr4_vgpr5
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%2:_(s96) = G_XOR %0, %1
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$vgpr0_vgpr1_vgpr2 = COPY %2
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...
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---
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name: test_xor_128
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK-LABEL: name: test_xor_128
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; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
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; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
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; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128)
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; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[UV]], [[UV2]]
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; CHECK: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[UV1]], [[UV3]]
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; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[XOR]](s64), [[XOR1]](s64)
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; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[MV]](s128)
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%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(s128) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
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%2:_(s128) = G_XOR %0, %1
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
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...
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---
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name: test_xor_s7
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body: |
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