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Revert r116983, which is breaking all the buildbots. 

llvm-svn: 116987
This commit is contained in:
Owen Anderson 2010-10-21 03:11:16 +00:00
parent f608ac4db9
commit 9e00f27e14
5 changed files with 6 additions and 41 deletions
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22
llvm/lib/Target/ARM/ARMScheduleA8.td
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@ -331,28 +331,6 @@ def CortexA8Itineraries : ProcessorItineraries<
InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<29, [A8_NPipe], 0>,
InstrStage<29, [A8_NLSPipe]>], [29, 1]>,
//
// Integer to Single-precision Move
InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<1, [A8_NPipe]>],
[2, 1]>,
//
// Integer to Double-precision Move
InstrItinData<IIC_fpMOVID, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<1, [A8_NPipe]>],
[2, 1, 1]>,
//
// Single-precision to Integer Move
InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<1, [A8_NPipe]>],
[20, 1]>,
//
// Double-precision to Integer Move
InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<1, [A8_NPipe]>],
[20, 20, 1]>,
//
// Single-precision FP Load
InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,

8
llvm/lib/Target/ARM/ARMScheduleA9.td
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@ -641,7 +641,7 @@ def CortexA9Itineraries : ProcessorItineraries<
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
InstrStage<1, [A9_NPipe]>],
[2, 1]>,
[1, 1]>,
//
// Double-precision to Integer Move
InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
@ -649,7 +649,7 @@ def CortexA9Itineraries : ProcessorItineraries<
InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
InstrStage<1, [A9_NPipe]>],
[2, 1, 1]>,
[1, 1, 1]>,
//
// Single-precision FP Load
InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
@ -1430,7 +1430,7 @@ def CortexA9Itineraries : ProcessorItineraries<
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe]>],
[1, 1]>,
[2, 1]>,
//
// Integer to Double-precision Move
InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
@ -1438,7 +1438,7 @@ def CortexA9Itineraries : ProcessorItineraries<
InstrStage<1, [A9_DRegsN], 0, Required>,
InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_NPipe]>],
[1, 1, 1]>,
[2, 1, 1]>,
//
// Single-precision to Integer Move
InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,

12
llvm/lib/Target/ARM/ARMScheduleV6.td
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@ -247,18 +247,6 @@ def ARMV6Itineraries : ProcessorItineraries<
// Double-precision FP SQRT
InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>,
//
// Integer to Single-precision Move
InstrItinData<IIC_fpMOVIS, [InstrStage<1, [V6_Pipe]>], [10, 1]>,
//
// Integer to Double-precision Move
InstrItinData<IIC_fpMOVID, [InstrStage<1, [V6_Pipe]>], [10, 1, 1]>,
//
// Single-precision to Integer Move
InstrItinData<IIC_fpMOVSI, [InstrStage<1, [V6_Pipe]>], [10, 1]>,
//
// Double-precision to Integer Move
InstrItinData<IIC_fpMOVDI, [InstrStage<1, [V6_Pipe]>], [10, 10, 1]>,
//
// Single-precision FP Load
InstrItinData<IIC_fpLoad32 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>,
//

2
llvm/test/CodeGen/ARM/fmscs.ll
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@ -19,6 +19,6 @@ entry:
; NFP0: vnmls.f32 s2, s1, s0
; CORTEXA8: test:
; CORTEXA8: vnmls.f32 s1, s2, s0
; CORTEXA8: vnmls.f32 s2, s1, s0
; CORTEXA9: test:
; CORTEXA9: vnmls.f32 s0, s1, s2

3
llvm/test/CodeGen/ARM/reg_sequence.ll
View File

@ -75,8 +75,7 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind {
; CHECK: t3:
; CHECK: vld3.8
; CHECK: vmul.i8
; CHECK: vmov r
; CHECK-NOT: vmov d
; CHECK-NOT: vmov
; CHECK: vst3.8
%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
%tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1]