forked from OSchip/llvm-project
parent
f32446fb65
commit
9df4aff86d
llvm/lib/Target/ARM
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@ -9845,7 +9845,6 @@ static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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uint64_t C;
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SDValue N0 = Op->getOperand(0);
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SDValue ConstVec = Op->getOperand(1);
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bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
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@ -9854,10 +9853,11 @@ static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
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uint32_t FloatBits = FloatTy.getSizeInBits();
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MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
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uint32_t IntBits = IntTy.getSizeInBits();
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unsigned NumLanes = Op.getValueType().getVectorNumElements();
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if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32 ||
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NumLanes > 4) {
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if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) {
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// These instructions only exist converting from f32 to i32. We can handle
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// smaller integers by generating an extra truncate, but larger ones would
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// be lossy. We also can't handle more then 4 lanes, since these intructions
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@ -9868,13 +9868,12 @@ static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG,
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SDLoc dl(N);
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unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
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Intrinsic::arm_neon_vcvtfp2fxu;
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SDValue FixConv = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl,
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NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
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DAG.getConstant(IntrinsicOpcode, dl, MVT::i32),
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N0,
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DAG.getConstant(Log2_64(C), dl, MVT::i32));
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SDValue FixConv = DAG.getNode(
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ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
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DAG.getConstant(IntrinsicOpcode, dl, MVT::i32), Op->getOperand(0),
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DAG.getConstant(Log2_64(C), dl, MVT::i32));
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if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
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if (IntBits < FloatBits)
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FixConv = DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), FixConv);
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return FixConv;
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