forked from OSchip/llvm-project
Rewrite LowerCallTo and Select(ISD::CALL) to properly handle float varargs
Tell the SelectionDAG ISel to expand SEXTLOAD of i1 and i8, rather than complicate the code in ISD::SEXTLOAD to do it by hand Combine the FP and Int ISD::LOAD codegen Generate better code for constant pool loads As a result, all of Shootout, and likely many other programs are now working. llvm-svn: 20945
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4c0780cf42
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@ -40,17 +40,20 @@ namespace {
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int ReturnAddrIndex; // FrameIndex for return slot.
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public:
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PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
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// Set up the TargetLowering object.
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// Set up the register classes.
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addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
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addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
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addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
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// PowerPC has no intrinsics for these particular operations
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setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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// PowerPC has an i16 but no i8 (or i1) SEXTLOAD
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setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
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setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
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computeRegisterProperties();
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}
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@ -244,7 +247,17 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
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unsigned ArgOffset = 24;
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unsigned GPR_remaining = 8;
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unsigned FPR_remaining = 13;
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std::vector<SDOperand> Stores;
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unsigned GPR_idx = 0, FPR_idx = 0;
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static const unsigned GPR[] = {
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PPC::R3, PPC::R4, PPC::R5, PPC::R6,
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PPC::R7, PPC::R8, PPC::R9, PPC::R10,
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};
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static const unsigned FPR[] = {
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PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
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PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
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};
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std::vector<SDOperand> MemOps;
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for (unsigned i = 0, e = Args.size(); i != e; ++i) {
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// PtrOff will be used to store the current argument to the stack if a
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// register cannot be found for it.
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@ -266,10 +279,12 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
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// FALL THROUGH
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case MVT::i32:
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if (GPR_remaining > 0) {
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args_to_use.push_back(Args[i].first);
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args_to_use.push_back(DAG.getCopyToReg(Chain, Args[i].first,
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GPR[GPR_idx]));
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--GPR_remaining;
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++GPR_idx;
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} else {
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Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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Args[i].first, PtrOff));
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}
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ArgOffset += 4;
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@ -283,19 +298,21 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
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Args[i].first, DAG.getConstant(1, MVT::i32));
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SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
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Args[i].first, DAG.getConstant(0, MVT::i32));
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args_to_use.push_back(Hi);
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if (GPR_remaining > 1) {
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args_to_use.push_back(Lo);
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GPR_remaining -= 2;
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args_to_use.push_back(DAG.getCopyToReg(Chain, Hi, GPR[GPR_idx]));
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--GPR_remaining;
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++GPR_idx;
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if (GPR_remaining > 0) {
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args_to_use.push_back(DAG.getCopyToReg(Chain, Lo, GPR[GPR_idx]));
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--GPR_remaining;
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++GPR_idx;
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} else {
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SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
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PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
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Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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Lo, PtrOff));
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--GPR_remaining;
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}
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} else {
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Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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Args[i].first, PtrOff));
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}
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ArgOffset += 8;
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@ -304,31 +321,49 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
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case MVT::f64:
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if (FPR_remaining > 0) {
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if (isVarArg) {
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// FIXME: Need FunctionType information so we can conditionally
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// store only the non-fixed arguments in a vararg function.
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Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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Args[i].first, PtrOff));
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// FIXME: Need a way to communicate to the ISD::CALL select code
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// that a particular argument is non-fixed so that we can load them
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// into the correct GPR to shadow the FPR
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// Float varargs are always shadowed in available integer registers
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if (GPR_remaining > 0) {
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SDOperand Load = DAG.getLoad(MVT::i32, Chain, PtrOff);
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MemOps.push_back(Load);
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args_to_use.push_back(DAG.getCopyToReg(Chain, Load,
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GPR[GPR_idx]));
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}
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args_to_use.push_back(Args[i].first);
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if (GPR_remaining > 1 && MVT::f64 == ArgVT) {
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SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
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PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
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SDOperand Load = DAG.getLoad(MVT::i32, Chain, PtrOff);
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MemOps.push_back(Load);
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args_to_use.push_back(DAG.getCopyToReg(Chain, Load,
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GPR[GPR_idx+1]));
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}
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}
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args_to_use.push_back(DAG.getCopyToReg(Chain, Args[i].first,
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FPR[FPR_idx]));
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--FPR_remaining;
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++FPR_idx;
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// If we have any FPRs remaining, we may also have GPRs remaining.
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// Args passed in FPRs consume either 1 (f32) or 2 (f64) available
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// GPRs.
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if (GPR_remaining > 0) --GPR_remaining;
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if (GPR_remaining > 0 && MVT::f64 == ArgVT) --GPR_remaining;
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if (GPR_remaining > 0) {
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--GPR_remaining;
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++GPR_idx;
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}
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if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
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--GPR_remaining;
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++GPR_idx;
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}
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} else {
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Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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Args[i].first, PtrOff));
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}
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ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
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break;
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}
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}
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if (!Stores.empty())
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
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if (!MemOps.empty())
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
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}
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std::vector<MVT::ValueType> RetVals;
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@ -591,38 +626,6 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
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return Result;
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case ISD::LOAD:
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case ISD::EXTLOAD: {
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MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
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Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
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// Make sure we generate both values.
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if (Result != 1)
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ExprMap[N.getValue(1)] = 1; // Generate the token
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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SDOperand Chain = N.getOperand(0);
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SDOperand Address = N.getOperand(1);
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Select(Chain);
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switch (TypeBeingLoaded) {
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default: assert(0 && "Cannot fp load this type!");
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case MVT::f32: Opc = PPC::LFS; break;
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case MVT::f64: Opc = PPC::LFD; break;
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}
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if(Address.getOpcode() == ISD::FrameIndex) {
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Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
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addFrameReference(BuildMI(BB, Opc, 2, Result), (int)Tmp1);
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} else {
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int offset;
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SelectAddr(Address, Tmp1, offset);
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BuildMI(BB, Opc, 2, Result).addSImm(offset).addReg(Tmp1);
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}
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return Result;
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}
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case ISD::ConstantFP:
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assert(0 && "ISD::ConstantFP Unimplemented");
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abort();
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@ -735,6 +738,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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if (DestType == MVT::f64 || DestType == MVT::f32)
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if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode)
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return SelectExprFP(N, Result);
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switch (opcode) {
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@ -796,10 +800,10 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::EXTLOAD:
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case ISD::ZEXTLOAD:
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case ISD::SEXTLOAD: {
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bool sext = (ISD::SEXTLOAD == opcode);
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bool byte = (MVT::i8 == Node->getValueType(0));
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MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
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Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
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bool sext = (ISD::SEXTLOAD == opcode);
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bool byte = (MVT::i8 == TypeBeingLoaded);
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// Make sure we generate both values.
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if (Result != 1)
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@ -812,22 +816,23 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Select(Chain);
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switch (TypeBeingLoaded) {
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default: assert(0 && "Cannot load this type!");
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default: Node->dump(); assert(0 && "Cannot load this type!");
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case MVT::i1: Opc = PPC::LBZ; break;
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case MVT::i8: Opc = PPC::LBZ; break;
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case MVT::i16: Opc = sext ? PPC::LHA : PPC::LHZ; break;
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case MVT::i32: Opc = PPC::LWZ; break;
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case MVT::f32: Opc = PPC::LFS; break;
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case MVT::f64: Opc = PPC::LFD; break;
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}
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// Since there's no load byte & sign extend instruction we have to split
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// byte SEXTLOADs into lbz + extsb. This requires we make a temp register.
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if (sext && byte) {
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Tmp3 = Result;
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Result = MakeReg(MVT::i32);
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} else {
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Tmp3 = 0; // Silence GCC warning.
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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Tmp1 = MakeReg(MVT::i32);
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int CPI = CP->getIndex();
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BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
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.addConstantPoolIndex(CPI);
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BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
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}
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if(Address.getOpcode() == ISD::FrameIndex) {
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else if(Address.getOpcode() == ISD::FrameIndex) {
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Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
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addFrameReference(BuildMI(BB, Opc, 2, Result), (int)Tmp1);
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} else {
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SelectAddr(Address, Tmp1, offset);
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BuildMI(BB, Opc, 2, Result).addSImm(offset).addReg(Tmp1);
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}
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if (sext && byte) {
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BuildMI(BB, PPC::EXTSB, 1, Tmp3).addReg(Result);
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Result = Tmp3;
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}
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return Result;
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}
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@ -847,62 +848,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Select(N.getOperand(0));
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ExprMap[N.getValue(Node->getNumValues()-1)] = 1;
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// get the virtual reg for each argument
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std::vector<unsigned> VRegs;
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for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
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VRegs.push_back(SelectExpr(N.getOperand(i)));
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// The ABI specifies that the first 32 bytes of args may be passed in GPRs,
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// and that 13 FPRs may also be used for passing any floating point args.
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int GPR_remaining = 8, FPR_remaining = 13;
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unsigned GPR_idx = 0, FPR_idx = 0;
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static const unsigned GPR[] = {
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PPC::R3, PPC::R4, PPC::R5, PPC::R6,
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PPC::R7, PPC::R8, PPC::R9, PPC::R10,
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};
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static const unsigned FPR[] = {
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PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
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PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
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PPC::F13
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};
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// move the vregs into the appropriate architected register or stack slot
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for(int i = 0, e = VRegs.size(); i < e; ++i) {
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unsigned OperandType = N.getOperand(i+2).getValueType();
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switch(OperandType) {
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default:
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Node->dump();
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N.getOperand(i).Val->dump();
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std::cerr << "Type for " << i << " is: " <<
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N.getOperand(i+2).getValueType() << "\n";
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assert(0 && "Unknown value type for call");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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if (GPR_remaining > 0)
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BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(VRegs[i])
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.addReg(VRegs[i]);
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break;
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case MVT::f32:
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case MVT::f64:
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if (FPR_remaining > 0) {
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BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(VRegs[i]);
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++FPR_idx;
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--FPR_remaining;
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}
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break;
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}
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// All arguments consume GPRs available for argument passing
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if (GPR_remaining > 0) {
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++GPR_idx;
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--GPR_remaining;
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}
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if (MVT::f64 == OperandType && GPR_remaining > 0) {
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++GPR_idx;
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--GPR_remaining;
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}
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}
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Select(N.getOperand(i));
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// Emit the correct call instruction based on the type of symbol called.
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if (GlobalAddressSDNode *GASD =
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